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ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 1 ? copyright 2013?2016 xilinx, inc. xi linx, the xilinx logo, artix, ise, kintex, spartan, virtex, vivado, zynq, and other design ated brands included herein are trademarks of xilinx in the united states and other countries. all othe r trademarks are the property of their respective owners. summary the xilinx? kintex? ultrascale? fpgas are available in -3, -2, -1, and -1l speed grades, with -3 having the highest performance. the -1l devices can operate at either of two v ccint voltages, 0.95v and 0.90v and are screened for lower maximum stat ic power. when operated at v ccint = 0.95v, the speed specification of a -1l device is the same as the -1 speed grade. when operated at v ccint = 0.90v, the -1l performance and static and dynamic power is reduced. dc and ac characteristics are specified in commer cial, extended, and indust rial temperature ranges. except the operating temperature range or unless otherwise noted, all the dc and ac electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1 speed grade industrial device are the same as for a -1 spee d grade commercial device). however, only selected speed grades and/or devices are av ailable in each temperature range. all supply voltage and junction temp erature specifications are representative of worst-case conditions. the parameters included are common to po pular designs and typical applications. this data sheet, part of an overall set of documentat ion on the ultrascale architecture-based devices, is available on the xilinx website at www.xilinx.com/ultrascale . dc characteristics kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 product specification table 1: absolute maximum ratings (1) symbol description min max units fpga logic v ccint internal supply voltage ?0.500 1.100 v v ccint_io (2) internal supply voltage for the i/o banks ?0.500 1.100 v v ccaux auxiliary supply voltage ?0.500 2.000 v v ccbram supply voltage for the block ram memories ?0.500 1.100 v v cco output drivers supply voltage for hr i/o banks ?0.500 3.400 v output drivers supply voltage for hp i/o banks ?0.500 2.000 v v ccaux_io (3) auxiliary supply voltage fo r the i/o banks ?0.500 2.000 v v ref input reference voltage ?0.500 2.000 v v in (4)(6)(7) i/o input voltage for hr i/o banks (5) ?0.400 v cco + 0.550 v i/o input voltage for hp i/o banks ?0.550 v cco + 0.550 v i/o input voltage (when v cco = 3.3v) for v ref and differential i/o standards except tmds_33 (8) ?0.400 2.625 v s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 2 v batt key memory battery backup supply ?0.500 2.000 v i dc available output current at the pad ?20 20 ma i rms available rms output current at the pad ?20 20 ma gth and gty transceivers v mgtavcc analog supply voltage for th e gth and gty transmitter and receiver circuits ?0.500 1.100 v v mgtavtt analog supply voltage for th e gth and gty transmitter and receiver termination circuits ?0.500 1.320 v v mgtvccaux auxiliary analog quad pll (qpll) voltage supply for the gth and gty transceivers ?0.500 1.935 v v mgtrefclk gth and gty transceiver reference clocks absolute input voltage ?0.500 1.320 v v mgtavttrcal analog supply voltage for the resistor calibration circuit of the gth and gty transceiver columns ?0.500 1.320 v v in receiver (rxp/rxn) and transmitter (txp/txn) absolute input voltage ?0.500 1.260 v i dcin-float dc input current for receiver input pins dc coupled rx termination = floating ?10ma i dcin-mgtavtt dc input current for receiver input pins dc coupled rx termination = v mgtavtt ?0 (9) ma i dcin-gnd dc input current for receiver input pins dc coupled rx termination = gnd ?0 (9) ma i dcin-prog dc input current for receiver input pins dc coupled rx termination = programmable ?0 (9) ma i dcout-float dc output current for transmitter pins dc coupled rx termination = floating ?10ma i dcout-mgtavtt dc output current for transmitter pins dc coupled rx termination = v mgtavtt ?6ma system monitor v ccadc system monitor supply relative to gndadc ?0.500 2.000 v v refp system monitor reference input relative to gndadc ?0.500 2.000 v temperature t stg storage temperature (ambient) ?65 150 c t sol maximum soldering temperature (10) ? 260 c table 1: absolute maximum ratings (1) (cont?d) symbol description min max units s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 3 t j maximum junction temperature (10) ? 125 c notes: 1. stresses beyond those listed under absolute maximum rati ngs might cause permanent dama ge to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not implied. expo sure to absolute maximum ratings condit ions for extended periods of time might affect device reliability. 2. v ccint_io must be connected to v ccint . 3. v ccaux_io must be connected to v ccaux . 4. the lower absolute voltage specification always applies. 5. if v cco is 3.3v, the maximum voltage is 3.4v. 6. for i/o operation, see the ultrascale architecture se lectio resources user guide ( ug571 ). 7. the maximum limit applied to dc signals. for maxi mum undershoot and overshoot ac specifications, see table 4 and table 5 . 8. see table 12 for tmds_33 specifications. 9. for more information on supported gth or gty transceiver terminations see the ultrascale architecture gth transceiver user guide ( ug576 ) or the ultrascale architecture gty transceiver user guide ( ug578 ). 10. for soldering guidelines and thermal considerations, see the ultrascale and ultrascale+ fpgas packaging and pinout specifications ( ug575 ). table 2: recommended oper ating conditions (1)(2) symbol description min typ max units fpga logic v ccint internal supply voltage 0.922 0.950 0.979 v for -1l (0.90v) devices: internal supply voltage 0.880 0.900 0.920 v for -3 (1.0v only) devices: internal supply voltage 0.970 1.000 1.030 v v ccint_io (3) internal supply voltage for the i/o banks 0.922 0.950 0.979 v for -1l (0.90v) devices: internal supply voltage for the i/o banks 0.880 0.900 0.920 v for -3 (1.0v only) devices: internal supply voltage for the i/o banks 0.970 1.000 1.030 v v ccbram block ram supply voltage 0.922 0.950 0.979 v for -3 (1.0v only) devices: block ram supply voltage 0.970 1.000 1.030 v v ccaux auxiliary supply voltage 1.746 1.800 1.854 v v cco (4)(5) supply voltage for hr i/o banks 1.140 ? 3.400 v supply voltage for hp i/o banks 0.950 ? 1.890 v v ccaux_io (6) auxiliary i/o supply voltage 1.746 1.800 1.854 v v in (7) i/o input voltage ?0.200 ? v cco + 0.200 v i/o input voltage (when v cco = 3.3v) for v ref and differential i/o standards except tmds_33 (8) . ? 0.400 2.625 v i in (9) maximum current through any pin in a powered or unpowered bank when forward biasing the clamp diode. ??10.000ma v batt (10) battery voltage 1.000 ? 1.890 v gth and gty transceivers v mgtavcc (11) analog supply voltage for the gth and gty transceivers (10) 0.970 1.000 1.030 v v mgtavtt (11) analog supply voltage for the gth and gty transmitter and receiver termination circuits 1.170 1.200 1.230 v v mgtvccaux (11) auxiliary analog qpll voltage supply for the transceivers 1.750 1.800 1.850 v table 1: absolute maximum ratings (1) (cont?d) symbol description min max units s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 4 v mgtavttrcal (11) analog supply voltage for the resistor calibration circuit of the gth and gty transceiver columns 1.170 1.200 1.230 v sysmon v ccadc sysmon supply relative to gndadc 1.746 1.800 1.854 v v refp externally supplied reference voltage 1.200 1.250 1.300 v temperature t j junction temperature operating range for commercial (c) temperature devices 0? 85 c junction temperature operating range for extended (e) temperature devices 0 ? 100 c junction temperature operating range for industrial (i) temperature devices ?40 ? 100 c notes: 1. all voltages are relative to ground. 2. for the design of the power distribution system consult ultrascale architectu re pcb design guide ( ug583 ). 3. v ccint_io must be connected to v ccint . 4. for v cco_0 , the minimum recomm ended operating voltage for power on and during configuration is 1.425v. after configuration, data is retained even if v cco drops to 0v. 5. includes v cco of 1.0v (hp i/o only), 1.2v, 1.35v, 1.5v, 1.8v, 2.5v (h r i/o only) at 5%, and 3.3v (hr i/o only) at +3/? 5%. 6. v ccaux_io must be connected to v ccaux . 7. the lower absolute voltage specification always applies. 8. see table 12 for tmds_33 specifications. 9. a total of 200 ma per 52-pin bank should not be exceeded. 10. v batt is required only when using bitstream encryption. if battery is not used, connect v batt to either ground or v ccaux . 11. each voltage listed requires filtering as described in ultrascale architecture gt h transceiver user guide ( ug576 ). table 2: recommended oper ating conditions (1)(2) (cont?d) symbol description min typ max units s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 5 table 3: dc characteristics over reco mmended operating conditions symbol description min typ (1) max units v drint data retention v ccint voltage (below which configuration data might be lost) 0.82 ? ? v v draux data retention v ccaux voltage (below which configuration data might be lost) 1.50 ? ? v i ref v ref leakage current per pin ? ? 15 a i l input or output leakage current per pin (sample-tested) ? ? 15 (2) a c in (3) die input capacitance at the pad (hp i/o) ? ? 3.75 pf die input capacitance at the pad (hr i/o) ? ? 7.00 pf i rpu pad pull-up (when selected) at v in =0v, v cco =3.3v 75 ? 175 a pad pull-up (when selected) at v in =0v, v cco =2.5v 50 ? 169 a pad pull-up (when selected) at v in =0v, v cco =1.8v 60 ? 678 a pad pull-up (when selected) at v in =0v, v cco =1.5v 30 ? 450 a pad pull-up (when selected) at v in =0v, v cco =1.2v 10 ? 262 a i rpd pad pull-down (when selected) at v in =3.3v 60 ? 190 a pad pull-down (when selected) at v in =1.8v 29 ? 685 a i ccadc analog supply current per sysmon instance in powered up state. ? ? 19.2 ma i batt (4) battery supply current ? ? 150 na calibrated programmable on-die te rmination (dci) in hp i/o banks (6) (measured per jedec specification) r (7) thevenin equivalent resistance of programmable input termination to v cco /2 where odt = rtt_40 ?10% (5) 40 +10% (5) thevenin equivalent resistance of programmable input termination to v cco /2 where odt = rtt_48 ?10% (5) 48 +10% (5) thevenin equivalent resistance of programmable input termination to v cco /2 where odt = rtt_60 ?10% (5) 60 +10% (5) programmable input termination to v cco where odt = rtt_40 ?10% (5) 40 +10% (5) programmable input termination to v cco where odt = rtt_48 ?10% (5) 48 +10% (5) programmable input termination to v cco where odt = rtt_60 ?10% (5) 60 +10% (5) programmable input termination to v cco where odt = rtt_120 ?10% (5) 120 +10% (5) programmable input termination to v cco where odt = rtt_240 ?10% (5) 240 +10% (5) s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 6 uncalibrated programmable on-die termination in hp i/os banks (measured per jedec specification) r (7) thevenin equivalent resistance of programmable input termination to v cco /2 where odt = rtt_40 ?50% 40 50% thevenin equivalent resistance of programmable input termination to v cco /2 where odt = rtt_48 ?50% 48 50% thevenin equivalent resistance of programmable input termination to v cco /2 where odt = rtt_60 ?50% 60 50% programmable input termination to v cco where odt = rtt_40 ?50% 40 50% programmable input termination to v cco where odt = rtt_48 ?50% 48 50% programmable input termination to v cco where odt = rtt_60 ?50% 60 50% programmable input termination to v cco where odt = rtt_120 ?50% 120 50% programmable input termination to v cco where odt = rtt_240 ?50% 240 50% uncalibrated programmable on-die termination in hr i/o banks (measured per jedec specification) r (7) thevenin equivalent resistance of programmable input termination to v cco /2 where odt = rtt_40 ?50% 40 50% thevenin equivalent resistance of programmable input termination to v cco /2 where odt = rtt_48 ?50% 48 50% thevenin equivalent resistance of programmable input termination to v cco /2 where odt = rtt_60 ?50% 60 50% internal v ref 50% v cco v cco x 0.49 v cco x 0.50 v cco x 0.51 v 70% v cco v cco x 0.69 v cco x 0.70 v cco x 0.71 v differential termination programmable differential termination (term_100) ? 100 ? n temperature diode ideality factor ? 1.002 ? ? r temperature diode series resistance ? 2 ? notes: 1. typical values are specified at nominal voltage, 25c. 2. for hp i/o banks with a v cco of 1.8v and separated v cco and v ccaux_io power supplies, the i l maximum current is 70 a. 3. this measurement represents the die capacitance at the pad, not including the package. 4. maximum value specified for worst case process at 25c. 5. if vrp resides at a different bank (dci cascade), the range increases to 15%. 6. vrp resistor tolerance is (240 1%) 7. on-die input termination resistance, for more information see the ultrascale architecture selectio resources user guide ( ug571 ). table 3: dc characteristics over reco mmended operating conditions (cont?d) symbol description min typ (1) max units s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 7 table 4: v in maximum allowed ac voltage overshoo t and undershoot for hr i/o banks (1) ac voltage overshoot % of ui at ?40c to 100c ac voltage undershoot % of ui at ?40c to 100c v cco + 0.30 100% ?0.30 100% v cco + 0.35 100% ?0.35 70.00% v cco + 0.40 100% ?0.40 27.00% v cco + 0.45 100% ?0.45 10.00% v cco + 0.50 85.00% ?0.50 5.00% v cco + 0.55 70.00% ?0.55 2.10% v cco + 0.60 46.60% ?0.60 1.50% v cco + 0.65 21.20% ?0.65 1.10% v cco + 0.70 9.75% ?0.70 0.60% v cco + 0.75 4.55% ?0.75 0.45% v cco + 0.80 2.15% ?0.80 0.20% v cco + 0.85 1.00% ?0.85 0.10% v cco + 0.90 0.50% ?0.90 0.05% v cco + 0.95 0.25% ?0.95 0.05% notes: 1. a total of 200 ma per bank should not be exceeded. table 5: v in maximum allowed ac voltage overshoo t and undershoot for hp i/o banks (1)(2) ac voltage overshoot % of ui at ?40c to 100c a c voltage undershoot % of ui at ?40c to 100c v cco + 0.05 100% ?0.05 100% v cco + 0.10 100% ?0.10 100% v cco + 0.15 100% ?0.15 100% v cco + 0.20 100% ?0.20 100% v cco + 0.25 100% ?0.25 100% v cco + 0.30 100% ?0.30 100% v cco + 0.35 92.00% ?0.35 92.00% v cco + 0.40 70.00% ?0.40 40.00% v cco + 0.45 30.00% ?0.45 15.00% v cco + 0.50 15.00% ?0.50 10.00% v cco + 0.55 10.00% ?0.55 4.00% v cco + 0.60 8.00% ?0.60 0.00% v cco + 0.65 6.00% ?0.65 0.00% v cco + 0.70 4.00% ?0.70 0.00% v cco + 0.75 2.00% ?0.75 0.00% v cco + 0.80 2.00% ?0.80 0.00% v cco + 0.85 2.00% ?0.85 0.00% notes: 1. a total of 200 ma per bank should not be exceeded. 2. for ui smaller than 20 s. s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 8 table 6: typical quiescent supply current symbol description device speed grade and v ccint operating voltages units 1.0v 0.95v 0.90v -3 -2 -1 -1l -1l i ccintq quiescent v ccint supply current xcku025 n/a 998 998 n/a n/a ma xcku035 1097 998 998 998 907 ma xcku040 1097 998 998 998 907 ma xcku060 1590 1446 1446 1446 1315 ma xcku085 3181 2893 2893 2893 2631 ma xcku095 n/a 2100 2100 n/a n/a ma xcku115 3181 2893 2893 2893 2631 ma i ccint_ioq quiescent current for v ccint_io supply xcku025 n/a 87 87 n/a n/a ma xcku0359887878777ma xcku0409887878777ma xcku060 118 105 105 105 93 ma xcku085 236 210 210 210 187 ma xcku095 n/a 143 143 n/a n/a ma xcku115 236 210 210 210 187 ma i ccoq quiescent v cco supply current xcku025 n/a 1 1 n/a n/a ma xcku03511111ma xcku04011111ma xcku06011111ma xcku08511111ma xcku095 n/a 1 1 n/a n/a ma xcku11511111ma i ccauxq quiescent v ccaux supply current xcku025 n/a 145 145 n/a n/a ma xcku035 145 145 145 145 145 ma xcku040 145 145 145 145 145 ma xcku060 188 188 188 188 188 ma xcku085 376 376 376 376 376 ma xcku095 n/a 273 273 n/a n/a ma xcku115 376 376 376 376 376 ma i ccaux_ioq quiescent v ccaux_io supply current xcku025 n/a 66 66 n/a n/a ma xcku0356666666666ma xcku0406666666666ma xcku0608383838383ma xcku085 165 165 165 165 165 ma xcku095 n/a 124 124 n/a n/a ma xcku115 165 165 165 165 165 ma s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 9 i ccbramq quiescent v ccbram supply current xcku025 n/a 39 39 n/a n/a ma xcku0354239393939ma xcku0404239393939ma xcku0607669696969ma xcku085 153 139 139 139 139 ma xcku095 n/a 111 111 n/a n/a ma xcku115 153 139 139 139 139 ma notes: 1. typical values are specified at nomina l voltage, 85c junction temperatures (t j ) with single-ended selectio? resources. 2. typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all i/o pins are 3-state and floating. 3. use the xilinx power estimator (xpe ) spreadsheet tool (download at www.xilinx.com/power ) to estimate static power consumption for conditions other than those specified. table 6: typical quiescent supply current (cont?d) symbol description device speed grade and v ccint operating voltages units 1.0v 0.95v 0.90v -3 -2 -1 -1l -1l s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 10 power-on/off power supply sequencing the recommended power-on sequence is v ccint /v ccint_io , v ccbram , v ccaux /v ccaux_io , and v cco to achieve minimum current draw and ensure that the i/os are 3-stated at power-on. the recommended power-off sequence is the reverse of the power-on sequence. if v ccint /v ccint_io and v ccbram have the same recommended voltage levels, th ey can be powered by the same supply and ramped simultaneously. v ccint_io must be connected to v ccint . if v ccaux /v ccaux_io and v cco have the same recommended voltage levels, they can be powered by the same supply and ramped simultaneously. v ccaux and v ccaux_io must be connected together. when the current minimums are met, the device powers on after the v ccint /v ccint_io , v ccbram , v ccaux /v ccaux_io , and v cco supplies have all passed through their power-on reset threshold voltages. the device mu st not be configured until after v ccint is applied. v ccadc and v ref can be powered at any time and have no power-up sequencing recommendations. the recommended power-on sequence to achieve mini mum current draw for the gth or gty transceivers is v ccint , v mgtavcc , v mgtavtt or v mgtavcc , v ccint , v mgtavtt . there is no recommended sequencing for v mgtvccaux . both v mgtavcc and v ccint can be ramped simultaneous ly. the recommended power-off sequence is the reverse of the power-on sequence to achieve minimum current draw. if these recommended sequences are not met, current drawn from v mgtavtt can be higher than specifications during power-up and power-down. s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 11 table 7 shows the minimum current, in addition to i ccq , that are required by kintex ultrascale fpgas for proper power-on and configuration. if the current minimums shown in table 6 and table 7 are met, the device powers on after all four supplies have passed through their power-on reset threshold voltages. the device must not be configured until after v ccint is applied. once initialized and configured, use the xilinx power estimator (xpe) tools to estimate current drain on these supplies. table 8 shows the power supply ramp time. table 7: power-on current by device device i ccintmin +i ccint_iomin i cco i ccauxmin +i ccaux_iomin i ccbrammin units xcku025 i ccintq +i ccint_ioq + 2400 i cco_0q + 100 i ccauxq +i ccaux_ioq +380 i ccbramq +50 ma xcku035 i ccintq +i ccint_ioq + 2400 i cco_0q + 100 i ccauxq +i ccaux_ioq +380 i ccbramq +50 ma xcku040 i ccintq +i ccint_ioq + 2400 i cco_0q + 100 i ccauxq +i ccaux_ioq +380 i ccbramq +50 ma xcku060 i ccintq +i ccint_ioq + 3284 i cco_0q + 137 i ccauxq +i ccaux_ioq +520 i ccbramq + 100 ma xcku085 i ccintq +i ccint_ioq + 6568 i cco_0q + 274 i ccauxq +i ccaux_ioq + 1040 i ccbramq + 137 ma xcku095 i ccintq +i ccint_ioq + 3300 i cco_0q +40 i ccauxq +i ccaux_ioq +400 i ccbramq + 150 ma xcku115 i ccintq +i ccint_ioq + 6568 i cco_0q + 274 i ccauxq +i ccaux_ioq + 1040 i ccbramq + 137 ma table 8: power supply ramp time symbol description min max units t vccint ramp time from gnd to 95% of v ccint 0.2 40 ms t vccint_io ramp time from gnd to 95% of v ccint_io 0.2 40 ms t vcco ramp time from gnd to 95% of v cco 0.2 40 ms t vccaux ramp time from gnd to 95% of v ccaux 0.2 40 ms t vccbram ramp time from gnd to 95% of v ccbram 0.2 40 ms t mgtavcc ramp time from gnd to 95% of v mgtavcc 0.2 40 ms t mgtavtt ramp time from gnd to 95% of v mgtavtt 0.2 40 ms t mgtvccaux ramp time from gnd to 95% of v mgtvccaux 0.2 40 ms s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 12 dc input and output levels values for v il and v ih are recommended input voltages. values for i ol and i oh are guaranteed over the recommended operating conditions at the v ol and v oh test points. only selected standards are tested. these are chosen to ensure that all standards meet th eir specifications. the selected standards are tested at a minimum v cco with the respective v ol and v oh voltage levels shown. other standards are sample tested. table 9: selectio dc input and output levels for hr i/o banks (1)(2) i/o standard v il v ih v ol v oh i ol i oh v, min v, max v, min v, max v, max v, min ma ma hstl_i ?0.300 v ref ? 0.100 v ref +0.100 v cco + 0.300 0.400 v cco ? 0.400 8.0 ?8.0 hstl_i_18 ?0.300 v ref ? 0.100 v ref +0.100 v cco + 0.300 0.400 v cco ? 0.400 8.0 ?8.0 hstl_ii ?0.300 v ref ? 0.100 v ref +0.100 v cco + 0.300 0.400 v cco ? 0.400 16.0 ?16.0 hstl_ii_18 ?0.300 v ref ? 0.100 v ref +0.100 v cco + 0.300 0.400 v cco ? 0.400 16.0 ?16.0 hsul_12 ?0.300 v ref ? 0.130 v ref +0.130 v cco + 0.300 20% v cco 80% v cco 0.1 ?0.1 lvcmos12 ?0.300 35% v cco 65% v cco v cco + 0.300 0.400 v cco ? 0.400 note 3 note 3 lvcmos15 ?0.300 35% v cco 65% v cco v cco + 0.300 0.450 v cco ? 0.450 note 4 note 4 lvcmos18 ?0.300 35% v cco 65% v cco v cco + 0.300 0.450 v cco ? 0.450 note 4 note 4 lvcmos25 ?0.300 0.700 1.700 v cco + 0.300 0.400 v cco ? 0.400 note 4 note 4 lvcmos33 ?0.300 0.800 2.000 3.400 0.400 v cco ? 0.400 note 4 note 4 lvttl ?0.300 0.800 2.000 3.400 0.400 2.400 note 4 note 4 sstl12 ?0.300 v ref ? 0.100 v ref +0.100 v cco + 0.300 v cco /2?0.150 v cco /2 + 0.150 14.25 ?14.25 sstl135 ?0.300 v ref ? 0.090 v ref +0.090 v cco + 0.300 v cco /2?0.150 v cco /2 + 0.150 13.0 ?13.0 sstl135_r ?0.300 v ref ? 0.090 v ref +0.090 v cco + 0.300 v cco /2?0.150 v cco /2 + 0.150 8.9 ?8.9 sstl15 ?0.300 v ref ? 0.100 v ref +0.100 v cco + 0.300 v cco /2?0.175 v cco /2 + 0.175 13.0 ?13.0 sstl15_r ?0.300 v ref ? 0.100 v ref +0.100 v cco + 0.300 v cco /2?0.175 v cco /2 + 0.175 8.9 ?8.9 sstl18_i ?0.300 v ref ? 0.125 v ref +0.125 v cco + 0.300 v cco /2?0.470 v cco /2 + 0.470 8.0 ?8.0 sstl18_ii ?0.300 v ref ? 0.125 v ref +0.125 v cco + 0.300 v cco /2?0.600 v cco /2 + 0.600 13.4 ?13.4 notes: 1. tested according to relevant specifications. 2. standards specified using the default i/o st andard configuration. for details, see the ultrascale architecture selectio resources user guide ( ug571 ). 3. supported drive stre ngths of 4, 8, or 12 ma in hr i/o banks. 4. supported drive streng ths of 4, 8, 12, or 16 ma in hr i/o banks. s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 13 table 10: selectio dc input and output levels for hp i/o banks (1)(2)(3) i/o standard v il v ih v ol v oh i ol i oh v, min v, max v, min v, max v, max v, min ma ma hstl_i ?0.300 v ref ? 0.100 v ref +0.100 v cco + 0.300 0.400 v cco ? 0.400 5.8 ?5.8 hstl_i_12 ?0.300 v ref ? 0.080 v ref +0.080 v cco + 0.300 25% v cco 75% v cco 4.1 ?4.1 hstl_i_18 ?0.300 v ref ? 0.100 v ref +0.100 v cco + 0.300 0.400 v cco ? 0.400 6.2 ?6.2 hsul_12 ?0.300 v ref ? 0.130 v ref +0.130 v cco + 0.300 20% v cco 80% v cco 0.1 ?0.1 lvcmos12 ?0.300 35% v cco 65% v cco v cco + 0.300 0.400 v cco ? 0.400 note 4 note 4 lvcmos15 ?0.300 35% v cco 65% v cco v cco + 0.300 0.450 v cco ? 0.450 note 5 note 5 lvcmos18 ?0.300 35% v cco 65% v cco v cco + 0.300 0.450 v cco ? 0.450 note 5 note 5 lvdci_15 ?0.300 35% v cco 65% v cco v cco + 0.300 0.450 v cco ? 0.450 7.0 ?7.0 lvdci_18 ?0.300 35% v cco 65% v cco v cco + 0.300 0.450 v cco ? 0.450 7.0 ?7.0 sstl12 ?0.300 v ref ? 0.100 v ref +0.100 v cco + 0.300 v cco /2?0.150 v cco /2 + 0.150 8.0 ?8.0 sstl135 ?0.300 v ref ? 0.090 v ref +0.090 v cco + 0.300 v cco /2?0.150 v cco /2 + 0.150 9.0 ?9.0 sstl15 ?0.300 v ref ? 0.100 v ref +0.100 v cco + 0.300 v cco /2?0.175 v cco /2 + 0.175 10.0 ?10.0 sstl18_i ?0.300 v ref ? 0.125 v ref +0.125 v cco + 0.300 v cco /2?0.470 v cco /2 + 0.470 7.0 ?7.0 notes: 1. tested according to relevant specifications. 2. standards specified using the default i/o st andard configuration. for details, see the ultrascale architecture selectio resources user guide ( ug571 ). 3. pod10 and pod12 dc input and output levels are shown in table 11 , table 16 , and table 17 . 4. supported drive streng ths of 2, 4, 6, or 8 ma in hp i/o banks. 5. supported drive strength s of 2, 4, 6, 8, or 12 ma in hp i/o banks. table 11: dc input levels for single-ended pod10 and pod12 i/o standards (1)(2) i/o standard v il v ih v, min v, max v, min v, max pod10 ?0.300 v ref ? 0.068 v ref +0.068 v cco + 0.300 pod12 ?0.300 v ref ? 0.068 v ref +0.068 v cco + 0.300 notes: 1. tested according to relevant specifications. 2. standards specified using the default i/o st andard configuration. for details, see the ultrascale architecture selectio resources user guide ( ug571 ). s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 14 table 12: differential selectio dc input and output levels i/o standard v icm (v) (1) v id (v) (2) v ocm (v) (3) v od (v) (4) min typ max min typ max min typ max min typ max blvds_25 0.300 1.200 1.425 0.100 ? ? ? 1.250 ? note 5 mini_lvds_25 0.300 1.200 v ccaux 0.200 0.400 0.600 1.000 1.200 1.485 0.300 0.450 0.600 sub_lvds 0.500 0.900 1.300 0.070 ? ? 0.700 0.900 1.100 0.100 0.150 0.200 lvpecl 0.300 1.200 1.425 0.100 0.350 0.600 ? ? ? ? ? ? ppds_25 0.200 0.900 v ccaux 0.100 0.250 0.400 0.500 0.950 1.400 0.100 0.250 0.400 rsds_25 0.300 0.900 1.500 0.100 0.350 0.600 1.000 1.200 1.485 0.100 0.350 0.600 slvs_400_18 0.070 0.200 0.330 0.140 ? 0.450 ? ? ? ? ? ? slvs_400_25 0.070 0.200 0.330 0.140 ? 0.450 ? ? ? ? ? ? tmds_33 2.700 2.965 3.230 0.150 0.675 1.200 v cco ? 0.405 v cco ? 0.300 v cco ? 0.190 0.400 0.600 0.800 notes: 1. v icm is the input common mode voltage. 2. v id is the input differential voltage (q ? q ). 3. v ocm is the output common mode voltage. 4. v od is the output differential voltage (q ? q ). 5. v od for blvds will vary significantly depending on topology and loading. 6. lvds_25 is specified in table 18 . 7. lvds is specified in table 19 . table 13: complementary differential selectio dc in put and output levels for hr i/o banks i/o standard v icm (v) (1) v id (v) (2) v ol (v) (3) v oh (v) (4) i ol i oh min typ max min max max min ma ma diff_hstl_i 0.300 0.750 1.125 0.100 ? 0.400 v cco ? 0.400 8.0 ?8.0 diff_hstl_i_18 0.300 0.900 1.425 0.100 ? 0.400 v cco ? 0.400 8.0 ?8.0 diff_hstl_ii 0.300 0.750 1.125 0.100 ? 0.400 v cco ? 0.400 16.0 ?16.0 diff_hstl_ii_18 0.300 0.900 1.425 0.100 ? 0.400 v cco ? 0.400 16.0 ?16.0 diff_hsul_12 0.300 0.600 0.850 0.100 ? 20% v cco 80% v cco 0.1 ?0.1 diff_sstl12 0.300 0.600 0.850 0.100 ? (v cco /2) ? 0.150 (v cco /2) + 0.150 14.25 ?14.25 diff_sstl135 0.300 0.675 1.000 0.100 ? (v cco /2) ? 0.150 (v cco /2) + 0.150 13.0 ?13.0 diff_sstl135_r 0.300 0.675 1.000 0.100 ? (v cco /2) ? 0.150 (v cco /2) + 0.150 8.9 ?8.9 diff_sstl15 0.300 0.750 1.125 0.100 ? (v cco /2) ? 0.175 (v cco /2) + 0.175 13.0 ?13.0 diff_sstl15_r 0.300 0.750 1.125 0.100 ? (v cco /2) ? 0.175 (v cco /2) + 0.175 8.9 ?8.9 diff_sstl18_i 0.300 0.900 1.425 0.100 ? (v cco /2) ? 0.470 (v cco /2) + 0.470 8.0 ?8.0 diff_sstl18_ii 0.300 0.900 1.425 0.100 ? (v cco /2) ? 0.600 (v cco /2) + 0.600 13.4 ?13.4 notes: 1. v icm is the input common mode voltage. 2. v id is the input differential voltage. 3. v ol is the single-ended low-output voltage. 4. v oh is the single-ended high-output voltage. s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 15 table 14: complementary differential selectio dc in put and output levels for hp i/o banks (1) i/o standard v icm (v) (2) v id (v) (3) v ol (v) (4) v oh (v) (5) i ol i oh min typ max min max max min ma ma diff_hstl_i 0.680 v cco /2 (v cco /2) + 0.150 0.100 ? 0.400 v cco ? 0.400 5.8 ?5.8 diff_hstl_i_12 0.400 x v cco v cco /2 0.600 x v cco 0.100 ? 0.250 x v cco 0.750 x v cco 4.1 ?4.1 diff_hstl_i_18 (v cco /2) ? 0.175 v cco /2 (v cco /2) + 0.175 0.100 ? 0.400 v cco ? 0.400 6.2 ?6.2 diff_hsul_12 (v cco /2) ? 0.120 v cco /2 (v cco /2) + 0.120 0.100 ? 20% v cco 80% v cco 0.1 ?0.1 diff_sstl12 (v cco /2) ? 0.150 v cco /2 (v cco /2) + 0.150 0.100 ? (v cco /2) ? 0.150 (v cco /2) + 0.150 8.0 ?8.0 diff_sstl135 (v cco /2) ? 0.150 v cco /2 (v cco /2) + 0.150 0.100 ? (v cco /2) ? 0.150 (v cco /2) + 0.150 9.0 ?9.0 diff_sstl15 (v cco /2) ? 0.175 v cco /2 (v cco /2) + 0.175 0.100 ? (v cco /2) ? 0.175 (v cco /2) + 0.175 10.0 ?10.0 diff_sstl18_i (v cco /2) ? 0.175 v cco /2 (v cco /2) + 0.175 0.100 ? (v cco /2) ? 0.470 (v cco /2) + 0.470 7.0 ?7.0 notes: 1. diff_pod10 and diff_pod12 hp i/o ba nk specifications are shown in table 15 , table 16 , and table 17 . 2. v icm is the input common mode voltage. 3. v id is the input differential voltage. 4. v ol is the single-ended low-output voltage. 5. v oh is the single-ended high-output voltage. table 15: dc input levels for differentia l pod10 and pod12 i/o standards (1)(2) i/o standard v icm (v) v id (v) min typ max min max diff_pod10 0.63 0.70 0.77 0.14 ? diff_pod12 0.76 0.84 0.92 0.16 ? notes: 1. tested according to relevant specifications. 2. standards specified using the default i/o st andard configuration. for details, see the ultrascale architecture selectio resources user guide ( ug571 ). table 16: dc output levels for sing le-ended and differential pod10 and pod12 standards (1)(2) symbol description v out min typ max units r ol pull-down resistance v om_dc (as described in table 17 ) 364044 r oh pull-up resistance v om_dc (as described in table 17 ) 364044 notes: 1. tested according to relevant specifications. 2. standards specified using the default i/o st andard configuration. for details, see the ultrascale architecture selectio resources user guide ( ug571 ). table 17: table 16 definitions for dc output levels for pod standards symbol description all devices units v om_dc dc output mid measurement level (for iv curve linearity) 0.8 x v cco v s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 16 lvds dc specifications (lvds_25) the lvds_25 standard is available in the hr i/o banks. see the ultrascale architectu re selectio resources user guide ( ug571 ) for more information. lvds dc specifications (lvds) the lvds standard is available in the hp i/o banks. see the ultrascale architecture selectio resources user guide ( ug571 ) for more information. table 18: lvds_25 dc specifications symbol dc parameter conditions min typ max units v cco supply voltage 2.375 2.500 2.625 v v odiff (1) differential output voltage: (q ? q ), q = high (q ?q), q =high r t =100 across q and q signals 247 350 600 mv v ocm (1) output common-mode voltage r t =100 across q and q signals 1.000 1.250 1.485 v v idiff differential input voltage: (q ? q ), q = high (q ?q), q =high 100 350 600 (2) mv v icm_dc (3) input common-mode voltage (dc coupling) 0.300 1.200 1.500 v v icm_ac (4) input common-mode voltage (ac coupling) 0.600 ? 1.100 v notes: 1. v ocm and v odiff values are for lvds_pre_emphasis = false. 2. maximum v idiff value is specified for the maximum v icm specification. with a lower v icm , a higher v diff is tolerated only when the recommended operating cond itions and oversh oot/undershoot v in specifications are maintained. 3. input common mode voltage for dc coupled co nfigurations. equalization = eq_none (default). 4. external input common mode voltage specification for ac coupled configurations . equalization = eq_level0, eq_level1, eq_level2, eq_level3, eq_level4. table 19: lvds dc specifications symbol dc parameter conditions min typ max units v cco supply voltage 1.710 1.800 1.890 v v odiff (1) differential output voltage (q ? q ), q = high (q ?q), q =high r t =100 across q and q signals 247 350 600 mv v ocm (1) output common-mode voltage r t =100 across q and q signals 1.000 1.250 1.425 v v idiff differential input voltage (q ? q ), q = high (q ?q), q =high 100 350 600 (2) mv v icm_dc (3) input common-mode voltage (dc coupling) 0.300 1.200 1.425 v v icm_ac (4) input common-mode voltage (ac coupling) 0.600 ? 1.100 v notes: 1. v ocm and v odiff values are for lvds_pre_emphasis = false. 2. maximum v idiff value is specified for the maximum v icm specification. with a lower v icm , a higher v diff is tolerated only when the recommended operating cond itions and oversh oot/undershoot v in specifications are maintained. 3. input common mode voltage for dc coupled co nfigurations. equalization = eq_none (default). 4. external input common mode voltage specification for ac coupled configurations . equalization = eq_level0, eq_level1, eq_level2, eq_level3, eq_level4. s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 17 ac switching characteristics all values represented in this data sheet are based on the speed specifications in the vivado? design suite as outlined in table 20 . switching characteristics are specified on a per-spee d-grade basis and can be designated as advance, preliminary, or production. each designation is defined as follows: advance product specification these specifications are based on simulations only an d are typically available so on after device design specifications are frozen. although speed grades with this designation are consider ed relatively stable and conservative, some under-rep orting might still occur. preliminary product specification these specifications are based on complete es (engin eering sample) silicon characterization. devices and speed grades with this designation are intended to gi ve a better indication of the expected performance of production silicon. the probability of under-repo rting delays is greatly reduced as compared to advance data. product specification these specifications are released once enough producti on silicon of a particular device family member has been characterized to provide full correlation be tween specifications and devices over numerous production lots. there is no under-reporting of dela ys, and customers receive formal notification of any subsequent changes. typically, the slowest speed grades transition to production before faster speed grades. testing of ac switching characteristics internal timing parameters are derived from meas uring internal test patt erns. all ac switching characteristics are representative of worst-case supply voltage and junction temperature conditions. for more specific, more precise, and worst-case guar anteed data, use the values reported by the static timing analyzer and back-annotate to the simulation net list. unless otherwise noted, values apply to all kintex ultrascale fpgas. table 20: speed specification version by device 2016.1 device 1.20 xcku025, xcku035, xcku040, xcku060 1.21 xcku085, xcku095, and xcku115 s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 18 speed grade designations since individual family members are produced at di fferent times, the migration from one category to another depends completely on the status of the fabrication process for each device. table 21 correlates the current status of the kintex ultras cale fpgas on a per speed grade basis. table 21: speed grade designations by device device speed grade and v ccint operating voltages advance preliminary production xcku025 -2 (0.95v) and -1 (0.95v) xcku035 -3 (1.0v), -2 (0.95v), -1 (0.95v), -1l (0.95v), and -1l (0.90v) (1) xcku040 -3 (1.0v), -2 (0.95v), -1 (0.95v), -1l (0.95v), and -1l (0.90v) (1) xcku060 -3 (1.0v), -2 (0.95v), -1 (0.95v), -1l (0.95v), and -1l (0.90v) (1) xcku085 -3 (1.0v), -2 (0.95v), -1 (0.95v), -1l (0.95v), and -1l (0.90v) (1) xcku095 -2 (0.95v) and -1 (0.95v) xcku115 -3 (1.0v), -2 (0.95v), -1 (0.95v), -1l (0.95v), and -1l (0.90v) (1) notes: 1. the lowest power -1l devices, where v ccint = 0.90v, are listed in the vivado design suite as -1lv. s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 19 production silicon and software status in some cases, a particular family member (and speed grade) is released to production before a speed specification is released with th e correct label (advance, prelimin ary, production). any labeling discrepancies are corrected in subseq uent speed specification releases. table 22 lists the production released kintex ultrascale fpgas, speed grade, and the minimum corresponding supported speed specification version an d vivado software revisions. the vivado software and speed specifications listed are the minimum releases required for production. all subsequent releases of software and speed specifications are valid. table 22: kintex ultrascale fpgas production soft ware and speed specification release device speed grade, temperature ranges, and v ccint operating voltages 1.0v 0.95v 0.90v -3e -2e, -2i -1c, -1i -1li -1li (2) xcku025 (1) n/a vivado tools 2015.3 v1.18 n/a n/a xcku035 (1) vivado tools 2015.2.1 v1.17 for fbva676 and ffva1156 packages vivado tools 2015.1 v1.15 for fbva676 and ffva1156 packages vivado tools 2015.3 v1.18 vivado tools 2015.3 v1.18 for fbva900 vivado tools 2015.4 v1.19 for sfva784 xcku040 (1) vivado tools 2015.2.1 v1.17 for fbva676 and ffva1156 packages vivado tools 2015.1 v1.15 for fbva676 and ffva1156 packages vivado tools 2015.3 v1.18 vivado tools 2015.3 v1.18 for fbva900 vivado tools 2015.4 v1.19 for sfva784 xcku060 (1) vivado tools 2015.4 v1.19 vivado tools 2015.2 v1.17 vivado tools 2015.3 v1.18 vivado tools 2015.4 v1.19 xcku085 (1) vivado tools 2015.4 v1.20 vivado tools 2015.3 v1.19 vivado tools 2016.1 v1.21 xcku095 n/a vivado tools 2015.3 v1.18 n/a n/a xcku115 (1) vivado tools 2015.4 v1.20 vivado tools 2015.2.1 v1.18 vivado tools 2016.1 v1.21 notes: 1. designs with these devices that use th e dedicated system monitor i2c (i2c_scl and i2c_sda) or pcie reset (perstn0 or perstn1) i/o where the bank 65 v cco = 3.3v must use vivado design suite 2015.4 or later. 2. the lowest power -1l devices, where v ccint = 0.90v, are listed in the vivado design suite as -1lv. s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 20 performance characteristics this section provides the performance characte ristics of some common functions and designs implemented in kintex ultrascale fpgas. these values are subject to the same guidelines as the ac switching characteristics, page 17 . in each table, the i/o bank type is either high performance (hp) or high range (hr). table 23: lvds component mode performance description i/o bank type speed grade and v ccint operating voltages units 1.0v 0.95v 0.90v -3 -2e -2i -1/-1l -1l lvds tx ddr (oserdes 4:1, 8:1) hp 1250 1250 1250 1250 1250 mb/s hr 1250 1250 1250 1000 1000 mb/s lvds tx sdr (oserdes 2:1, 4:1) hp 625 625 625 625 625 mb/s hr 625 625 625 500 500 mb/s lvds rx ddr (iserdes 1:4, 1:8) (1) hp 1250 1250 1250 1250 1250 mb/s hr 1250 1250 1250 1000 1000 mb/s lvds rx sdr (iserdes 1:2, 1:4) (1) hp 625 625 625 625 625 mb/s hr 625 625 625 500 500 mb/s notes: 1. lvds receivers are typically bounded with certain applications where specif ic dynamic phase-alignment (dpa) or phase-tracking algorithms are used to achieve maximum performance. table 24: lvds native mode performance (1) description i/o bank type speed grade and v ccint operating voltages units 1.0v 0.95v 0.90v -3 -2e -2i -1/-1l -1l lvds tx ddr (tx_bitslice 4:1, 8:1) hp 1600 1600 1600 1400 1400 mb/s hr 1250 1250 1250 1250 1250 mb/s lvds tx sdr (tx_bitslice 2:1, 4:1) hp 800 800 800 700 700 mb/s hr 625 625 625 625 625 mb/s lvds rx ddr (rx_bitslice 1:4, 1:8) (2) hp 1600 1600 1600 1400 1400 mb/s hr 1250 1250 1250 1250 1250 mb/s lvds rx sdr (rx_bitslice 1:2, 1:4) (2) hp 800 800 800 700 700 mb/s hr 625 625 625 625 625 mb/s notes: 1. native mode is supported through the high-speed selectio interface wizard available with the vivado design suite. 2. lvds receivers are typically bounded with certain applications where specif ic dynamic phase-alignment (dpa) or phase-tracking algorithms are used to achieve maximum performance. s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 21 table 26 provides the maximum data rates for applicable memory standards using the kintex ultrascale fpgas memory phy. refer to memory interfaces for the complete list of memory interface standards supported and detailed specifications. the final perf ormance of the memory interface is determined through a complete design implemented in the viva do design suite, following guidelines in the ultrascale architecture pc b design guide ( ug583 ), electrical analysis, and ch aracterization of the system. table 25: lvds native-mode 1000base-x support (1) description i/o bank type speed grade and v ccint operating voltages 1.0v 0.95v 0.90v -3 -2e -2i -1/-1l -1l 1000base-x hp yes yes yes yes yes notes: 1. 1000base-x support is based on the ieee standard for csma/cd access meth od and physical layer specifications (ieee std 802.3-2008). table 26: maximum physical interface (phy) rate fo r memory interfaces by i/o and package memory standard i/o bank type package dram type speed grade, temperature ranges, and v ccint operating voltages units 1.0v 0.95v 0.90v -3e -2e -2i -1c/i /li -1l ddr4 hp all ff packages all fl packages fbva900 single rank component 2400 2400 2400 2133 2133 mb/s 1 rank dimm (1)(2) 2133 2133 2133 1866 1866 2 rank dimm (1)(3) 1866 1866 1866 1600 1600 4 rank dimm (1)(4) 1333 1333 1333 n/a n/a fbva676 sfva784 single rank component 2133 2133 2133 1866 1866 1 rank dimm (1)(2) 1866 1866 1866 1600 1600 2 rank dimm (1)(3) 1600 1600 1600 1333 1333 ddr3 hp all ff packages all fl packages fbva676 fbva900 single rank component 2133 2133 2133 1866 1866 mb/s 1 rank dimm (1)(2) 1866 1866 1866 1600 1600 2 rank dimm (1)(3) 1600 1600 1600 1333 1333 4 rank dimm (1)(4) 1066 1066 1066 800 800 sfva784 single rank component 1866 1866 1866 1600 1600 1 rank dimm (1)(2) 1600 1600 1600 1333 1333 2 rank dimm (1)(3) 1333 1333 1333 1066 1066 4 rank dimm (1)(4) 800 800 800 606 606 hr all single rank component 1333 (5) 1066 1066 s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 22 iob pad input, output, and 3-state table 27 (high-range iob (hr)) and table 28 (high-performance iob (hp)) summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays. ? t inbuf_delay_pad_i is the delay from iob pad through the inpu t buffer to the i-pin of an iob pad. the delay varies depending on the capa bility of the selectio input buffer. ? t outbuf_delay_o_pad is the delay from the o pin to the iob pad through the output buffer of an iob pad. the delay varies depending on the ca pability of the selectio output buffer. ddr3l hp all ff packages all fl packages fbva676 fbva900 single rank component 1866 1866 1866 1600 1600 mb/s 1 rank dimm (1)(2) 1600 1600 1600 1333 1333 2 rank dimm (1)(3) 1333 1333 1333 1066 1066 4 rank dimm (1)(4) 800 800 800 606 606 sfva784 single rank component 1600 1600 1600 1600 1600 1 rank dimm (1)(2) 1333 1333 1333 1333 1333 2 rank dimm (1)(3) 1066 1066 1066 1066 1066 4 rank dimm (1)(4) 606 606 606 606 606 hr all single rank component 1066 1066 1066 800 800 qdr ii+ (6) all all single rank component 633 600 600 550 550 mhz qdriv-xp hp all single rank component 800 800 800 667 667 rldram iii hp all ff packages all fl packages fbva676 fbva900 single rank component 1066 1066 1066 933 933 sfva784 933 933 933 800 800 lpddr3 hp all single rank component 1600 1600 1600 1600 1600 mb/s hr all single rank component 1066 1066 1066 1066 1066 notes: 1. dual in-line memory module (dimm) incl udes rdimm, sodimm, udimm, and lrdimm. 2. includes: 1 rank 1 slot, ddp 2 rank, lrdimm 2 or 4 rank 1 slot. 3. includes: 2 rank 1 slot, 1 rank 2 slot, lrdimm 2 rank 2 slot. 4. includes: 2 rank 2 slot, 4 rank 1 slot. 5. memory device must be rated at 1600 or above. 6. the qdrii+ performance spec ifications are for burst-leng th 4 (bl = 4) implementations. table 26: maximum physical interface (phy) rate fo r memory interfaces by i/o and package memory standard i/o bank type package dram type speed grade, temperature ranges, and v ccint operating voltages units 1.0v 0.95v 0.90v -3e -2e -2i -1c/i /li -1l s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 23 ? t outbuf_delay_td_pad is the delay from the t pin to the iob pad through the output buffer of an iob pad, when 3-state is disabled. the delay varies de pending on the selectio capability of the output buffer. in hp i/o banks, the internal dci termi nation turn-on time is always faster than t outbuf_delay_td_pad when the dcitermdisable pin is used. in hr i/o banks, the on-die termination turn-on time is always faster than t outbuf_delay_td_pad when the intermdisable pin is used. table 27: iob high range (hr) sw itching characteristics i/o standards t inbuf_delay_pad_i t outbuf_delay_o_pad t outbuf_delay_td_pad units 1.0v 0.95v 0.9v 1.0v 0.95v 0.9v 1.0v 0.95v 0.9v -3 -2 -1/ -1l -1l -3 -2 -1/ -1l -1l -3 -2 -1/ -1l -1l blvds_25 0.46 0.58 0.64 0.64 1.37 1.37 1.62 1.62 1.39 1.40 1.66 1.66 ns diff_hstl_i_18_f 0.42 0.53 0.57 0.57 0.71 0.71 0.90 0.91 0.82 0.82 1.06 1.06 ns diff_hstl_i_18_s 0.42 0.53 0.57 0.57 0.83 0.83 1.02 1.03 0.93 0.94 1.16 1.16 ns diff_hstl_i_f 0.42 0.53 0.57 0.57 0.73 0.73 0.92 0.93 0.90 0.90 1.14 1.14 ns diff_hstl_i_s 0.42 0.53 0.57 0.57 0.77 0.77 0.96 0.96 0.95 0.98 1.23 1.23 ns diff_hstl_ii_18_f 0.42 0.53 0.57 0.57 0.80 0.80 0.99 1.00 0.95 0.98 1.23 1.23 ns diff_hstl_ii_18_s 0.42 0.53 0.57 0.57 0.83 0.83 1.03 1.03 1.01 1.03 1.28 1.28 ns diff_hstl_ii_f 0.42 0.53 0.57 0.57 0.71 0.71 0.91 0.91 0.87 0.87 1.11 1.11 ns diff_hstl_ii_s 0.42 0.53 0.57 0.57 0.80 0.80 0.99 0.99 0.95 0.96 1.20 1.20 ns diff_hsul_12_f 0.42 0.53 0.57 0.57 0.73 0.73 0.92 0.92 0.73 0.73 0.92 0.92 ns diff_hsul_12_s 0.42 0.53 0.57 0.57 0.82 0.82 1.01 1.02 0.82 0.82 1.01 1.02 ns diff_sstl12_f 0.42 0.53 0.57 0.57 0.70 0.70 0.89 0.89 0.81 0.81 1.02 1.02 ns diff_sstl12_s 0.42 0.53 0.57 0.57 1.04 1.04 1.26 1.26 1.04 1.04 1.26 1.26 ns diff_sstl135_f 0.42 0.53 0.57 0.57 0.70 0.70 0.88 0.88 0.86 0.87 1.09 1.09 ns diff_sstl135_s 0.42 0.53 0.57 0.57 0.77 0.77 0.96 0.96 0.93 0.94 1.18 1.18 ns diff_sstl135_r_f 0.42 0.53 0.57 0.57 0.72 0.72 0.91 0.91 0.83 0.84 1.06 1.06 ns diff_sstl135_r_s 0.42 0.53 0.57 0.57 0.80 0.80 1.00 1.00 0.93 0.93 1.17 1.17 ns diff_sstl15_f 0.42 0.53 0.57 0.57 0.66 0.66 0.85 0.85 0.81 0.82 1.05 1.05 ns diff_sstl15_s 0.42 0.53 0.57 0.57 0.78 0.78 0.98 0.98 0.96 0.96 1.20 1.21 ns diff_sstl15_r_f 0.42 0.53 0.57 0.57 0.73 0.73 0.92 0.92 0.86 0.86 1.09 1.09 ns diff_sstl15_r_s 0.42 0.53 0.57 0.57 0.81 0.81 1.01 1.02 0.93 0.94 1.18 1.18 ns diff_sstl18_i_f 0.42 0.53 0.57 0.57 0.74 0.74 0.94 0.94 0.92 0.93 1.18 1.19 ns diff_sstl18_i_s 0.42 0.53 0.57 0.57 0.86 0.86 1.05 1.06 0.86 0.86 1.05 1.06 ns diff_sstl18_ii_f 0.42 0.53 0.57 0.57 0.71 0.71 0.90 0.90 0.87 0.88 1.11 1.12 ns diff_sstl18_ii_s 0.42 0.53 0.57 0.57 0.83 0.83 1.03 1.03 0.99 1.04 1.29 1.30 ns hstl_i_18_f 0.52 0.55 0.59 0.59 0.73 0.73 0.93 0.93 0.84 0.84 1.08 1.08 ns hstl_i_18_s 0.52 0.55 0.59 0.59 0.85 0.85 1.05 1.05 0.95 0.96 1.18 1.18 ns hstl_i_f 0.52 0.55 0.59 0.59 0.75 0.75 0.94 0.95 0.92 0.92 1.16 1.17 ns hstl_i_s 0.52 0.55 0.59 0.59 0.79 0.79 0.98 0.99 0.97 1.00 1.25 1.25 ns hstl_ii_18_f 0.52 0.55 0.59 0.59 0.82 0.82 1.01 1.02 0.97 1.00 1.25 1.25 ns hstl_ii_18_s 0.52 0.55 0.59 0.59 0.85 0.85 1.05 1.05 1.03 1.05 1.30 1.30 ns hstl_ii_f 0.52 0.55 0.59 0.59 0.73 0.73 0.93 0.93 0.89 0.90 1.13 1.13 ns hstl_ii_s 0.52 0.55 0.59 0.59 0.82 0.82 1.01 1.02 0.98 0.98 1.22 1.22 ns s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 24 hsul_12_f 0.52 0.55 0.59 0.59 0.75 0.75 0.94 0.95 0.75 0.75 0.94 0.95 ns hsul_12_s 0.52 0.55 0.59 0.59 0.84 0.84 1.04 1.04 0.96 0.97 1.15 1.15 ns lvcmos12_f_12 0.76 0.95 0.95 0.95 0.95 0.95 1.16 1.16 0.95 0.95 1.16 1.16 ns lvcmos12_f_4 0.76 0.95 0.95 0.95 1.13 1.16 1.39 1.39 1.13 1.16 1.39 1.39 ns lvcmos12_f_8 0.76 0.95 0.95 0.95 0.97 0.97 1.19 1.19 0.97 0.97 1.19 1.19 ns lvcmos12_s_12 0.76 0.95 0.95 0.95 1.06 1.06 1.28 1.28 1.06 1.06 1.28 1.28 ns lvcmos12_s_4 0.76 0.95 0.95 0.95 1.27 1.36 1.60 1.60 1.27 1.36 1.60 1.60 ns lvcmos12_s_8 0.76 0.95 0.95 0.95 1.10 1.10 1.32 1.32 1.10 1.10 1.32 1.32 ns lvcmos15_f_12 0.68 0.82 0.87 0.88 0.96 0.96 1.18 1.18 0.96 0.96 1.18 1.18 ns lvcmos15_f_16 0.68 0.82 0.87 0.88 0.94 0.94 1.15 1.15 0.94 0.94 1.17 1.17 ns lvcmos15_f_4 0.68 0.82 0.87 0.88 1.15 1.15 1.38 1.39 1.15 1.15 1.38 1.39 ns lvcmos15_f_8 0.68 0.82 0.87 0.88 1.02 1.02 1.24 1.24 1.02 1.02 1.24 1.24 ns lvcmos15_s_12 0.68 0.82 0.87 0.88 1.07 1.07 1.29 1.30 1.07 1.07 1.29 1.30 ns lvcmos15_s_16 0.68 0.82 0.87 0.88 1.04 1.04 1.26 1.27 1.04 1.04 1.26 1.27 ns lvcmos15_s_4 0.68 0.82 0.87 0.88 1.28 1.29 1.53 1.54 1.28 1.29 1.53 1.54 ns lvcmos15_s_8 0.68 0.82 0.87 0.88 1.11 1.11 1.34 1.34 1.11 1.11 1.34 1.34 ns lvcmos18_f_12 0.64 0.76 0.79 0.80 1.04 1.04 1.25 1.26 1.04 1.04 1.25 1.26 ns lvcmos18_f_16 0.64 0.76 0.79 0.80 1.00 1.00 1.21 1.22 1.00 1.00 1.21 1.22 ns lvcmos18_f_4 0.64 0.76 0.79 0.80 1.17 1.17 1.41 1.41 1.17 1.17 1.41 1.41 ns lvcmos18_f_8 0.64 0.76 0.79 0.80 1.10 1.10 1.33 1.33 1.10 1.10 1.33 1.33 ns lvcmos18_s_12 0.64 0.76 0.79 0.80 1.11 1.11 1.34 1.35 1.11 1.11 1.34 1.35 ns lvcmos18_s_16 0.64 0.76 0.79 0.80 1.11 1.11 1.34 1.34 1.11 1.11 1.34 1.34 ns lvcmos18_s_4 0.64 0.76 0.79 0.80 1.32 1.32 1.58 1.58 1.32 1.32 1.58 1.58 ns lvcmos18_s_8 0.64 0.76 0.79 0.80 1.18 1.18 1.38 1.38 1.18 1.18 1.38 1.38 ns lvcmos25_f_12 0.83 0.85 0.90 0.91 1.54 1.54 1.81 1.81 1.54 1.54 1.81 1.81 ns lvcmos25_f_16 0.83 0.85 0.90 0.91 1.56 1.59 1.88 1.88 1.56 1.59 1.88 1.88 ns lvcmos25_f_4 0.83 0.85 0.90 0.91 2.24 2.24 2.56 2.56 2.24 2.24 2.56 2.56 ns lvcmos25_f_8 0.83 0.85 0.90 0.91 1.67 1.67 1.95 1.95 1.67 1.67 1.95 1.95 ns lvcmos25_s_12 0.83 0.85 0.90 0.91 2.05 2.14 2.47 2.47 2.05 2.14 2.47 2.47 ns lvcmos25_s_16 0.83 0.85 0.90 0.91 1.84 1.89 2.19 2.19 1.84 1.89 2.19 2.19 ns lvcmos25_s_4 0.83 0.85 0.90 0.91 3.23 3.27 3.68 3.68 3.23 3.27 3.68 3.68 ns lvcmos25_s_8 0.83 0.85 0.90 0.91 2.11 2.15 2.47 2.47 2.11 2.15 2.47 2.47 ns lvcmos33_f_12 0.96 0.97 1.03 1.03 1.98 1.98 2.24 2.24 1.98 1.98 2.24 2.24 ns lvcmos33_f_16 0.96 0.97 1.03 1.03 1.79 1.79 2.09 2.09 1.79 1.79 2.09 2.09 ns lvcmos33_f_4 0.96 0.97 1.03 1.03 2.34 2.34 2.63 2.63 2.34 2.34 2.63 2.63 ns lvcmos33_f_8 0.96 0.97 1.03 1.03 2.05 2.05 2.32 2.33 2.05 2.05 2.32 2.33 ns lvcmos33_s_12 0.96 0.97 1.03 1.03 2.13 2.13 2.48 2.48 2.13 2.13 2.48 2.48 ns lvcmos33_s_16 0.96 0.97 1.03 1.03 2.11 2.11 2.43 2.43 2.11 2.11 2.43 2.43 ns table 27: iob high range (hr) switching characteristics (cont?d) i/o standards t inbuf_delay_pad_i t outbuf_delay_o_pad t outbuf_delay_td_pad units 1.0v 0.95v 0.9v 1.0v 0.95v 0.9v 1.0v 0.95v 0.9v -3 -2 -1/ -1l -1l -3 -2 -1/ -1l -1l -3 -2 -1/ -1l -1l s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 25 lvcmos33_s_4 0.96 0.97 1.03 1.03 3.23 3.23 3.67 3.67 3.23 3.23 3.67 3.67 ns lvcmos33_s_8 0.96 0.97 1.03 1.03 2.28 2.28 2.55 2.55 2.66 2.67 2.78 2.78 ns lvds_25 0.45 0.58 0.62 0.63 0.80 0.83 0.95 0.95 105.74 105.74 105.85 105.85 ns lvpecl 0.43 0.57 0.62 0.63 n/a n/a n/a n/a n/a n/a n/a n/a ns lvttl_f_12 1.04 1.04 1.05 1.06 1.83 1.83 2.10 2.10 1.83 1.83 2.10 2.10 ns lvttl_f_16 1.04 1.04 1.05 1.06 1.79 1.79 2.06 2.06 1.79 1.79 2.06 2.06 ns lvttl_f_4 1.04 1.04 1.05 1.06 2.34 2.34 2.63 2.63 2.34 2.34 2.63 2.63 ns lvttl_f_8 1.04 1.04 1.05 1.06 1.97 1.97 2.22 2.23 1.97 1.97 2.22 2.23 ns lvttl_s_12 1.04 1.04 1.05 1.06 1.90 1.90 2.19 2.19 1.96 1.97 2.19 2.19 ns lvttl_s_16 1.04 1.04 1.05 1.06 2.07 2.07 2.40 2.40 2.07 2.07 2.40 2.40 ns lvttl_s_4 1.04 1.04 1.05 1.06 3.23 3.23 3.67 3.67 3.23 3.23 3.67 3.67 ns lvttl_s_8 1.04 1.04 1.05 1.06 2.22 2.22 2.47 2.47 2.22 2.37 2.50 2.51 ns mini_lvds_25 0.45 0.58 0.62 0.63 0.80 0.83 0.95 0.95 105.74 105.74 105.85 105.85 ns ppds_25 0.45 0.58 0.62 0.63 0.80 0.83 0.95 0.95 105.74 105.74 105.85 105.85 ns rsds_25 0.45 0.58 0.62 0.63 0.80 0.83 0.95 0.95 105.74 105.74 105.85 105.85 ns slvs_400_25 0.45 0.58 0.62 0.63 n/a n/a n/a n/a n/a n/a n/a n/a ns sstl12_f 0.52 0.55 0.59 0.59 0.72 0.72 0.91 0.91 0.83 0.83 1.04 1.04 ns sstl12_s 0.52 0.55 0.59 0.59 0.78 0.78 0.97 0.98 0.88 0.88 1.11 1.11 ns sstl135_f 0.52 0.55 0.59 0.59 0.72 0.72 0.90 0.91 0.88 0.89 1.11 1.11 ns sstl135_s 0.52 0.55 0.59 0.59 0.77 0.77 0.97 0.97 0.94 0.94 1.18 1.18 ns sstl135_r_f 0.52 0.55 0.59 0.59 0.74 0.74 0.93 0.93 0.85 0.86 1.08 1.08 ns sstl135_r_s 0.52 0.55 0.59 0.59 0.82 0.82 1.02 1.03 0.95 0.96 1.19 1.19 ns sstl15_f 0.52 0.55 0.59 0.59 0.68 0.68 0.87 0.87 0.83 0.84 1.07 1.07 ns sstl15_s 0.52 0.55 0.59 0.59 0.80 0.80 1.00 1.01 0.98 0.99 1.23 1.23 ns sstl15_r_f 0.52 0.55 0.59 0.59 0.75 0.75 0.94 0.94 0.88 0.89 1.11 1.11 ns sstl15_r_s 0.52 0.55 0.59 0.59 0.83 0.83 1.04 1.04 0.95 0.96 1.20 1.21 ns sstl18_i_f 0.52 0.55 0.59 0.59 0.76 0.76 0.96 0.96 0.94 0.95 1.21 1.21 ns sstl18_i_s 0.52 0.55 0.59 0.59 0.88 0.88 1.08 1.08 0.88 0.88 1.08 1.08 ns sstl18_ii_f 0.52 0.55 0.59 0.59 0.73 0.73 0.92 0.92 0.89 0.90 1.14 1.14 ns sstl18_ii_s 0.52 0.55 0.59 0.59 0.85 0.85 1.05 1.05 1.01 1.06 1.32 1.32 ns sub_lvds 0.45 0.58 0.62 0.63 0.80 0.83 0.95 0.95 105.74 105.74 105.85 105.85 ns tmds_33 0.57 0.65 0.73 0.74 0.80 0.83 0.95 0.95 105.74 105.74 105.85 105.85 ns table 27: iob high range (hr) switching characteristics (cont?d) i/o standards t inbuf_delay_pad_i t outbuf_delay_o_pad t outbuf_delay_td_pad units 1.0v 0.95v 0.9v 1.0v 0.95v 0.9v 1.0v 0.95v 0.9v -3 -2 -1/ -1l -1l -3 -2 -1/ -1l -1l -3 -2 -1/ -1l -1l s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 26 table 28: iob high performance (hp) switching characteristics i/o standards t inbuf_delay_pad_i t outbuf_delay_o_pad t outbuf_delay_td_pad units 1.0v 0.95v 0.9v 1.0v 0.95v 0.9v 1.0v 0.95v 0.9v -3 -2 -1/ -1l -1l -3 -2 -1/ -1l -1l -3 -2 -1/ -1l -1l diff_hstl_i_12_f 0.43 0.48 0.55 0.55 0.46 0.50 0.54 0.54 0.54 0.62 0.68 0.68 ns diff_hstl_i_12_m 0.43 0.48 0.55 0.55 0.50 0.55 0.60 0.60 0.60 0.68 0.76 0.76 ns diff_hstl_i_12_s 0.43 0.48 0.55 0.55 0.56 0.61 0.67 0.67 0.67 0.76 0.85 0.85 ns diff_hstl_i_18_f 0.43 0.48 0.55 0.55 0.45 0.49 0.53 0.53 0.53 0.61 0.68 0.68 ns diff_hstl_i_18_m 0.43 0.48 0.55 0.55 0.50 0.55 0.59 0.59 0.59 0.68 0.76 0.76 ns diff_hstl_i_18_s 0.43 0.48 0.55 0.55 0.56 0.62 0.67 0.67 0.67 0.77 0.86 0.86 ns diff_hstl_i_dci_12_f 0.43 0.48 0.55 0.55 0.46 0.50 0.54 0.54 0.54 0.62 0.68 0.68 ns diff_hstl_i_dci_12_m 0.43 0.48 0.55 0.55 0.50 0.55 0.60 0.60 0.60 0.68 0.76 0.76 ns diff_hstl_i_dci_12_s 0.43 0.48 0.55 0.55 0.56 0.61 0.67 0.67 0.67 0.76 0.85 0.85 ns diff_hstl_i_dci_18_f 0.43 0.48 0.55 0.55 0.45 0.49 0.53 0.53 0.53 0.61 0.68 0.68 ns diff_hstl_i_dci_18_m 0.43 0.48 0.55 0.55 0.50 0.55 0.59 0.59 0.59 0.68 0.76 0.76 ns diff_hstl_i_dci_18_s 0.43 0.48 0.55 0.55 0.56 0.62 0.67 0.67 0.67 0.77 0.86 0.86 ns diff_hstl_i_dci_f 0.43 0.48 0.55 0.55 0.46 0.50 0.54 0.54 0.54 0.62 0.68 0.68 ns diff_hstl_i_dci_m 0.43 0.48 0.55 0.55 0.50 0.55 0.60 0.60 0.60 0.68 0.76 0.76 ns diff_hstl_i_dci_s 0.43 0.48 0.55 0.55 0.56 0.61 0.67 0.67 0.67 0.76 0.85 0.85 ns diff_hstl_i_f 0.43 0.48 0.55 0.55 0.46 0.50 0.54 0.54 0.54 0.62 0.68 0.68 ns diff_hstl_i_m 0.43 0.48 0.55 0.55 0.50 0.55 0.60 0.60 0.60 0.68 0.76 0.76 ns diff_hstl_i_s 0.43 0.48 0.55 0.55 0.56 0.61 0.67 0.67 0.67 0.76 0.85 0.85 ns diff_hsul_12_dci_f 0.43 0.48 0.55 0.55 0.46 0.50 0.54 0.54 0.54 0.62 0.68 0.68 ns diff_hsul_12_dci_m 0.43 0.48 0.55 0.55 0.50 0.55 0.60 0.60 0.60 0.68 0.76 0.76 ns diff_hsul_12_dci_s 0.43 0.48 0.55 0.55 0.56 0.61 0.67 0.67 0.67 0.76 0.85 0.85 ns diff_hsul_12_f 0.43 0.48 0.55 0.55 0.46 0.50 0.54 0.54 0.54 0.62 0.68 0.68 ns diff_hsul_12_m 0.43 0.48 0.55 0.55 0.50 0.55 0.60 0.60 0.60 0.68 0.76 0.76 ns diff_hsul_12_s 0.43 0.48 0.55 0.55 0.56 0.61 0.67 0.67 0.67 0.76 0.85 0.85 ns diff_pod10_dci_f 0.430.480.550.550.460.500.550.550.580.650.730.73 ns diff_pod10_dci_m 0.430.480.550.550.520.580.630.630.620.710.790.79 ns diff_pod10_dci_s 0.430.480.550.550.610.680.740.740.690.790.880.88 ns diff_pod10_f 0.430.480.550.550.460.500.550.550.580.650.730.73 ns diff_pod10_m 0.430.480.550.550.520.580.630.630.620.710.790.79 ns diff_pod10_s 0.430.480.550.550.610.680.740.740.690.790.880.88 ns diff_pod12_dci_f 0.430.480.550.550.460.500.550.550.580.650.730.73 ns diff_pod12_dci_m 0.430.480.550.550.520.580.630.630.620.710.790.79 ns diff_pod12_dci_s 0.430.480.550.550.610.680.740.740.690.790.880.88 ns diff_pod12_f 0.430.480.550.550.460.500.550.550.580.650.730.73 ns diff_pod12_m 0.430.480.550.550.520.580.630.630.620.710.790.79 ns diff_pod12_s 0.430.480.550.550.610.680.740.740.690.790.880.88 ns diff_sstl12_dci_f 0.430.480.550.550.460.500.540.540.540.620.680.68 ns diff_sstl12_dci_m 0.430.480.550.550.500.550.600.600.600.680.760.76 ns s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 27 diff_sstl12_dci_s 0.430.480.550.550.560.610.670.670.670.760.850.85 ns diff_sstl12_f 0.430.480.550.550.460.500.540.540.540.620.680.68 ns diff_sstl12_m 0.430.480.550.550.500.550.600.600.600.680.760.76 ns diff_sstl12_s 0.430.480.550.550.560.610.670.670.670.760.850.85 ns diff_sstl135_dci_f 0.43 0.48 0.55 0.55 0.46 0.50 0.54 0.54 0.54 0.62 0.69 0.69 ns diff_sstl135_dci_m 0.43 0.48 0.55 0.55 0.50 0.55 0.60 0.60 0.60 0.68 0.76 0.76 ns diff_sstl135_dci_s 0.43 0.48 0.55 0.55 0.56 0.61 0.67 0.67 0.67 0.76 0.85 0.85 ns diff_sstl135_f 0.43 0.48 0.55 0.55 0.46 0.50 0.54 0.54 0.54 0.62 0.69 0.69 ns diff_sstl135_m 0.43 0.48 0.55 0.55 0.50 0.55 0.60 0.60 0.60 0.68 0.76 0.76 ns diff_sstl135_s 0.43 0.48 0.55 0.55 0.56 0.61 0.67 0.67 0.67 0.76 0.85 0.85 ns diff_sstl15_dci_f 0.430.480.550.550.460.500.540.540.540.620.680.68 ns diff_sstl15_dci_m 0.430.480.550.550.500.550.600.600.600.680.760.76 ns diff_sstl15_dci_s 0.430.480.550.550.560.610.670.670.670.760.850.85 ns diff_sstl15_f 0.430.480.550.550.460.500.540.540.540.620.680.68 ns diff_sstl15_m 0.430.480.550.550.500.550.600.600.600.680.760.76 ns diff_sstl15_s 0.430.480.550.550.560.610.670.670.670.760.850.85 ns diff_sstl18_i_dci_f 0.430.480.550.550.450.490.530.530.530.610.680.68 ns diff_sstl18_i_dci_m 0.430.480.550.550.500.550.590.590.590.680.760.76 ns diff_sstl18_i_dci_s 0.430.480.550.550.560.620.670.670.670.770.860.86 ns diff_sstl18_i_f 0.430.480.550.550.450.490.530.530.530.610.680.68 ns diff_sstl18_i_m 0.430.480.550.550.500.550.590.590.590.680.760.76 ns diff_sstl18_i_s 0.430.480.550.550.560.620.670.670.670.770.860.86 ns hslvdci_15_f 0.43 0.46 0.52 0.52 0.48 0.53 0.56 0.56 0.57 0.64 0.71 0.71 ns hslvdci_15_m 0.43 0.46 0.52 0.52 0.53 0.57 0.62 0.62 0.62 0.71 0.79 0.79 ns hslvdci_15_s 0.43 0.46 0.52 0.52 0.58 0.64 0.69 0.69 0.70 0.79 0.88 0.88 ns hslvdci_18_f 0.43 0.46 0.52 0.52 0.48 0.53 0.57 0.57 0.57 0.65 0.71 0.71 ns hslvdci_18_m 0.43 0.46 0.52 0.52 0.52 0.57 0.62 0.62 0.62 0.71 0.79 0.79 ns hslvdci_18_s 0.43 0.46 0.52 0.52 0.58 0.64 0.69 0.69 0.70 0.80 0.90 0.90 ns hstl_i_12_f 0.43 0.46 0.52 0.52 0.48 0.52 0.56 0.56 0.56 0.63 0.70 0.70 ns hstl_i_12_m 0.43 0.46 0.52 0.52 0.52 0.57 0.61 0.61 0.61 0.70 0.78 0.78 ns hstl_i_12_s 0.43 0.46 0.52 0.52 0.57 0.63 0.68 0.68 0.69 0.78 0.87 0.87 ns hstl_i_18_f 0.43 0.46 0.52 0.52 0.47 0.51 0.55 0.55 0.55 0.63 0.70 0.70 ns hstl_i_18_m 0.43 0.46 0.52 0.52 0.52 0.57 0.61 0.61 0.61 0.70 0.78 0.78 ns hstl_i_18_s 0.43 0.46 0.52 0.52 0.58 0.63 0.69 0.69 0.69 0.78 0.88 0.88 ns hstl_i_dci_12_f 0.43 0.46 0.52 0.52 0.48 0.52 0.56 0.56 0.56 0.63 0.70 0.70 ns hstl_i_dci_12_m 0.43 0.46 0.52 0.52 0.52 0.57 0.61 0.61 0.61 0.70 0.78 0.78 ns hstl_i_dci_12_s 0.43 0.46 0.52 0.52 0.57 0.63 0.68 0.68 0.69 0.78 0.87 0.87 ns hstl_i_dci_18_f 0.43 0.46 0.52 0.52 0.47 0.51 0.55 0.55 0.55 0.63 0.70 0.70 ns table 28: iob high performance (hp) switching characteristics (cont?d) i/o standards t inbuf_delay_pad_i t outbuf_delay_o_pad t outbuf_delay_td_pad units 1.0v 0.95v 0.9v 1.0v 0.95v 0.9v 1.0v 0.95v 0.9v -3 -2 -1/ -1l -1l -3 -2 -1/ -1l -1l -3 -2 -1/ -1l -1l s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 28 hstl_i_dci_18_m 0.43 0.46 0.52 0.52 0.52 0.57 0.61 0.61 0.61 0.70 0.78 0.78 ns hstl_i_dci_18_s 0.43 0.46 0.52 0.52 0.58 0.63 0.69 0.69 0.69 0.78 0.88 0.88 ns hstl_i_dci_f 0.43 0.46 0.52 0.52 0.47 0.52 0.56 0.56 0.56 0.63 0.70 0.70 ns hstl_i_dci_m 0.43 0.46 0.52 0.52 0.52 0.57 0.61 0.61 0.61 0.70 0.78 0.78 ns hstl_i_dci_s 0.43 0.46 0.52 0.52 0.57 0.63 0.68 0.68 0.69 0.78 0.87 0.87 ns hstl_i_f 0.43 0.46 0.52 0.52 0.47 0.52 0.56 0.56 0.56 0.63 0.70 0.70 ns hstl_i_m 0.43 0.46 0.52 0.52 0.52 0.57 0.61 0.61 0.61 0.70 0.78 0.78 ns hstl_i_s 0.43 0.46 0.52 0.52 0.57 0.63 0.68 0.68 0.69 0.78 0.87 0.87 ns hsul_12_dci_f 0.43 0.46 0.52 0.52 0.48 0.52 0.56 0.56 0.56 0.63 0.70 0.70 ns hsul_12_dci_m 0.43 0.46 0.52 0.52 0.52 0.57 0.61 0.61 0.61 0.70 0.78 0.78 ns hsul_12_dci_s 0.43 0.46 0.52 0.52 0.57 0.63 0.68 0.68 0.69 0.78 0.87 0.87 ns hsul_12_f 0.43 0.46 0.52 0.52 0.48 0.52 0.56 0.56 0.56 0.63 0.70 0.70 ns hsul_12_m 0.43 0.46 0.52 0.52 0.52 0.57 0.61 0.61 0.61 0.70 0.78 0.78 ns hsul_12_s 0.43 0.46 0.52 0.52 0.57 0.63 0.68 0.68 0.69 0.78 0.87 0.87 ns lvcmos12_f_2 0.56 0.66 0.74 0.74 0.67 0.73 0.79 0.79 0.67 0.73 0.79 0.79 ns lvcmos12_f_4 0.56 0.66 0.74 0.74 0.63 0.68 0.73 0.73 0.63 0.68 0.73 0.73 ns lvcmos12_f_6 0.56 0.66 0.74 0.74 0.59 0.64 0.69 0.69 0.59 0.65 0.72 0.72 ns lvcmos12_f_8 0.56 0.66 0.74 0.74 0.57 0.63 0.67 0.67 0.59 0.66 0.72 0.72 ns lvcmos12_m_2 0.56 0.66 0.74 0.74 0.72 0.79 0.85 0.85 0.72 0.79 0.85 0.85 ns lvcmos12_m_4 0.56 0.66 0.74 0.74 0.66 0.71 0.77 0.77 0.66 0.71 0.77 0.77 ns lvcmos12_m_6 0.56 0.66 0.74 0.74 0.62 0.67 0.72 0.72 0.62 0.69 0.75 0.75 ns lvcmos12_m_8 0.56 0.66 0.74 0.74 0.62 0.67 0.72 0.72 0.64 0.71 0.78 0.78 ns lvcmos12_s_2 0.56 0.66 0.74 0.74 0.77 0.89 0.96 0.96 0.77 0.89 0.96 0.96 ns lvcmos12_s_4 0.56 0.66 0.74 0.74 0.68 0.74 0.79 0.79 0.68 0.74 0.79 0.79 ns lvcmos12_s_6 0.56 0.66 0.74 0.74 0.66 0.72 0.78 0.78 0.66 0.72 0.79 0.79 ns lvcmos12_s_8 0.56 0.66 0.74 0.74 0.66 0.72 0.77 0.77 0.67 0.74 0.82 0.82 ns lvcmos15_f_12 0.450.520.580.580.610.660.710.710.660.730.810.81 ns lvcmos15_f_2 0.45 0.52 0.58 0.58 0.73 0.77 0.83 0.83 0.73 0.77 0.83 0.83 ns lvcmos15_f_4 0.45 0.52 0.58 0.58 0.69 0.73 0.78 0.78 0.69 0.73 0.78 0.78 ns lvcmos15_f_6 0.45 0.52 0.58 0.58 0.63 0.68 0.73 0.73 0.63 0.70 0.77 0.77 ns lvcmos15_f_8 0.45 0.52 0.58 0.58 0.61 0.66 0.72 0.72 0.63 0.71 0.78 0.78 ns lvcmos15_m_12 0.450.520.580.580.630.690.750.750.670.770.850.85 ns lvcmos15_m_2 0.45 0.52 0.58 0.58 0.77 0.80 0.86 0.86 0.77 0.80 0.86 0.86 ns lvcmos15_m_4 0.45 0.52 0.58 0.58 0.72 0.76 0.82 0.82 0.72 0.76 0.82 0.82 ns lvcmos15_m_6 0.45 0.52 0.58 0.58 0.67 0.72 0.78 0.78 0.67 0.74 0.82 0.82 ns lvcmos15_m_8 0.45 0.52 0.58 0.58 0.65 0.71 0.76 0.76 0.65 0.76 0.83 0.83 ns lvcmos15_s_12 0.450.520.580.580.650.700.750.750.670.750.830.83 ns lvcmos15_s_2 0.45 0.52 0.58 0.58 0.78 0.85 0.91 0.91 0.78 0.85 0.91 0.91 ns table 28: iob high performance (hp) switching characteristics (cont?d) i/o standards t inbuf_delay_pad_i t outbuf_delay_o_pad t outbuf_delay_td_pad units 1.0v 0.95v 0.9v 1.0v 0.95v 0.9v 1.0v 0.95v 0.9v -3 -2 -1/ -1l -1l -3 -2 -1/ -1l -1l -3 -2 -1/ -1l -1l s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 29 lvcmos15_s_4 0.45 0.52 0.58 0.58 0.74 0.78 0.84 0.84 0.74 0.78 0.84 0.84 ns lvcmos15_s_6 0.45 0.52 0.58 0.58 0.72 0.76 0.82 0.82 0.72 0.76 0.84 0.84 ns lvcmos15_s_8 0.45 0.52 0.58 0.58 0.68 0.73 0.79 0.79 0.68 0.75 0.83 0.83 ns lvcmos18_f_12 0.430.490.540.540.670.720.780.780.670.810.900.90 ns lvcmos18_f_2 0.43 0.49 0.54 0.54 0.94 1.07 1.15 1.15 0.94 1.07 1.15 1.15 ns lvcmos18_f_4 0.43 0.49 0.54 0.54 0.78 0.82 0.89 0.89 0.78 0.82 0.89 0.89 ns lvcmos18_f_6 0.43 0.49 0.54 0.54 0.72 0.77 0.83 0.83 0.72 0.79 0.88 0.88 ns lvcmos18_f_8 0.43 0.49 0.54 0.54 0.70 0.75 0.81 0.81 0.72 0.81 0.89 0.89 ns lvcmos18_m_12 0.430.490.540.540.700.760.810.810.740.830.920.92 ns lvcmos18_m_2 0.43 0.49 0.54 0.54 0.99 1.10 1.19 1.19 0.99 1.10 1.19 1.19 ns lvcmos18_m_4 0.43 0.49 0.54 0.54 0.82 0.86 0.92 0.92 0.82 0.86 0.92 0.92 ns lvcmos18_m_6 0.43 0.49 0.54 0.54 0.75 0.80 0.87 0.87 0.75 0.81 0.90 0.90 ns lvcmos18_m_8 0.43 0.49 0.54 0.54 0.73 0.78 0.85 0.85 0.73 0.83 0.92 0.92 ns lvcmos18_s_12 0.430.490.540.540.740.780.840.840.760.830.920.92 ns lvcmos18_s_2 0.43 0.49 0.54 0.54 1.05 1.16 1.25 1.25 1.05 1.16 1.25 1.25 ns lvcmos18_s_4 0.43 0.49 0.54 0.54 0.83 0.86 0.93 0.93 0.83 0.86 0.93 0.93 ns lvcmos18_s_6 0.43 0.49 0.54 0.54 0.79 0.82 0.89 0.89 0.79 0.82 0.90 0.90 ns lvcmos18_s_8 0.43 0.49 0.54 0.54 0.75 0.80 0.86 0.86 0.75 0.82 0.90 0.90 ns lvdci_15_f 0.45 0.52 0.58 0.58 0.48 0.53 0.56 0.56 0.57 0.64 0.71 0.71 ns lvdci_15_m 0.45 0.52 0.58 0.58 0.53 0.57 0.62 0.62 0.62 0.71 0.79 0.79 ns lvdci_15_s 0.45 0.52 0.58 0.58 0.58 0.64 0.69 0.69 0.70 0.79 0.88 0.88 ns lvdci_18_f 0.43 0.49 0.54 0.54 0.48 0.53 0.57 0.57 0.57 0.65 0.71 0.71 ns lvdci_18_m 0.43 0.49 0.54 0.54 0.52 0.57 0.62 0.62 0.62 0.71 0.79 0.79 ns lvdci_18_s 0.43 0.49 0.54 0.54 0.58 0.64 0.69 0.69 0.70 0.80 0.90 0.90 ns lvds 0.42 0.46 0.51 0.51 0.57 0.67 0.72 0.72 890.24 890.26 890.28 890.28 ns pod10_dci_f 0.430.460.520.520.480.520.560.560.590.670.740.74 ns pod10_dci_m 0.430.460.520.520.540.600.650.650.640.730.810.81 ns pod10_dci_s 0.430.460.520.520.630.690.760.760.710.810.890.89 ns pod10_f 0.430.460.520.520.480.520.560.560.590.670.740.74 ns pod10_m 0.430.460.520.520.540.600.650.650.640.730.810.81 ns pod10_s 0.430.460.520.520.630.690.760.760.710.810.890.89 ns pod12_dci_f 0.430.460.520.520.480.520.560.560.590.670.740.74 ns pod12_dci_m 0.430.460.520.520.540.600.650.650.640.730.810.81 ns pod12_dci_s 0.430.460.520.520.630.690.760.760.710.810.890.89 ns pod12_f 0.430.460.520.520.480.520.560.560.590.670.740.74 ns pod12_m 0.430.460.520.520.540.600.650.650.640.730.810.81 ns pod12_s 0.430.460.520.520.630.690.760.760.710.810.890.89 ns slvs_400_18 0.42 0.46 0.51 0.51 n/a n/a n/a n/a n/a n/a n/a n/a ns table 28: iob high performance (hp) switching characteristics (cont?d) i/o standards t inbuf_delay_pad_i t outbuf_delay_o_pad t outbuf_delay_td_pad units 1.0v 0.95v 0.9v 1.0v 0.95v 0.9v 1.0v 0.95v 0.9v -3 -2 -1/ -1l -1l -3 -2 -1/ -1l -1l -3 -2 -1/ -1l -1l s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 30 sstl12_dci_f 0.430.460.520.520.480.520.560.560.560.630.700.70 ns sstl12_dci_m 0.430.460.520.520.520.570.610.610.610.700.780.78 ns sstl12_dci_s 0.430.460.520.520.570.630.680.680.690.780.870.87 ns sstl12_f 0.430.460.520.520.480.520.560.560.560.630.700.70 ns sstl12_m 0.430.460.520.520.520.570.610.610.610.700.780.78 ns sstl12_s 0.430.460.520.520.570.630.680.680.690.780.870.87 ns sstl135_dci_f 0.43 0.46 0.52 0.52 0.48 0.52 0.56 0.56 0.56 0.64 0.70 0.70 ns sstl135_dci_m 0.43 0.46 0.52 0.52 0.52 0.57 0.61 0.61 0.61 0.70 0.78 0.78 ns sstl135_dci_s 0.43 0.46 0.52 0.52 0.57 0.63 0.68 0.68 0.69 0.78 0.87 0.87 ns sstl135_f 0.43 0.46 0.52 0.52 0.48 0.52 0.56 0.56 0.56 0.64 0.70 0.70 ns sstl135_m 0.43 0.46 0.52 0.52 0.52 0.57 0.61 0.61 0.61 0.70 0.78 0.78 ns sstl135_s 0.43 0.46 0.52 0.52 0.57 0.63 0.68 0.68 0.69 0.78 0.87 0.87 ns sstl15_dci_f 0.430.460.520.520.470.520.560.560.560.630.700.70 ns sstl15_dci_m 0.430.460.520.520.520.570.610.610.610.700.780.78 ns sstl15_dci_s 0.430.460.520.520.570.630.680.680.690.780.870.87 ns sstl15_f 0.430.460.520.520.470.520.560.560.560.630.700.70 ns sstl15_m 0.430.460.520.520.520.570.610.610.610.700.780.78 ns sstl15_s 0.430.460.520.520.570.630.680.680.690.780.870.87 ns sstl18_i_dci_f 0.430.460.520.520.470.510.550.550.550.630.700.70 ns sstl18_i_dci_m 0.430.460.520.520.520.570.610.610.610.700.780.78 ns sstl18_i_dci_s 0.430.460.520.520.580.630.690.690.690.780.880.88 ns sstl18_i_f 0.430.460.520.520.470.510.550.550.550.630.700.70 ns sstl18_i_m 0.430.460.520.520.520.570.610.610.610.700.780.78 ns sstl18_i_s 0.430.460.520.520.580.630.690.690.690.780.880.88 ns sub_lvds 0.42 0.46 0.51 0.51 0.57 0.67 0.72 0.72 890.24 890.26 890.28 890.28 ns table 28: iob high performance (hp) switching characteristics (cont?d) i/o standards t inbuf_delay_pad_i t outbuf_delay_o_pad t outbuf_delay_td_pad units 1.0v 0.95v 0.9v 1.0v 0.95v 0.9v 1.0v 0.95v 0.9v -3 -2 -1/ -1l -1l -3 -2 -1/ -1l -1l -3 -2 -1/ -1l -1l s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 31 table 29 specifies the values of t outbuf_delay_te_pad and t inbuf_delay_ibufdis_o . t outbuf_delay_te_pad is the delay from the t pin to the iob pad through the output buffer of an iob pad, when 3-state is enabled (i.e., a high impedance state). t inbuf_delay_ibufdis_o is the iob delay from ibufdisable to o output. in hp i/o banks, the internal dci termination tu rn-off time is always faster than t outbuf_delay_te_pad when the dcitermdisable pin is used. in hr i/o banks, the in ternal in_term termination turn-off time is always faster than t outbuf_delay_te_pad when the intermdisable pin is used. i/o standard adjustment measurement methodology input delay measurements table 30 shows the test setup parameters used for measuring input delay. table 29: iob 3-state output switching characteristics symbol description speed grade and v ccint operating voltages units 1.0v 0.95v 0.90v -3 -2 -1/-1l -1l t outbuf_delay_te_pad (1) t input to pad high-impedance for hr i/o banks 1.37 1.52 1.69 1.69 ns t input to pad high-impedance for hp i/o banks 0.62 0.71 0.78 0.78 ns t inbuf_delay_ibufdis_o ibuf turn-on time from ibufdisable to o output for hr i/o banks 0.47 0.65 0.68 0.68 ns ibuf turn-on time from ibufdisable to o output for hp i/o banks 1.06 1.21 1.49 1.49 ns notes: 1. the t outbuf_delay_te_pad values are applicable to single-ended i/o standa rds. for true differential standards, the values are larger. use the vivado timing report for the mo st accurate timing values for your configuration. table 30: input delay measurement methodology description i/o standard attribute v l (1)(2) v h (1)(2) v meas (1)(4)(6) v ref (1)(3)(5) lvcmos, 1.2v lvcmos12 0.1 1.1 0.6 ? lvcmos, lvdci, hslvdci, 1.5v lvcmos15, lvdci_15, hslvdci_15 0.1 1.4 0.75 ? lvcmos, lvdci, hslvdci, 1.8v lvcmos18, lvdci_18, hslvdci_18 0.1 1.7 0.9 ? lvcmos, 2.5v lvcmos25 0.1 2.4 1.25 ? lvcmos, 3.3v lvcmos33 0.1 3.2 1.65 ? lvttl, 3.3v lvttl 0.1 3.2 1.65 ? hstl (high-speed transceiver logic), class i, 1.2v hstl_i_12 v ref ?0.5 v ref +0.5 v ref 0.60 hstl, class i and ii, 1.5v hstl_i, hstl_ii v ref ?0.65 v ref +0.65 v ref 0.75 hstl, class i and ii, 1.8v hstl_i_18, hstl_ii_18 v ref ?0.8 v ref +0.8 v ref 0.90 hsul (high-speed unterminated logic), 1.2v hsul_12 v ref ?0.5 v ref +0.5 v ref 0.60 sstl (stub series terminated logic), 1.2v sstl12 v ref ?0.5 v ref +0.5 v ref 0.60 s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 32 sstl, 1.35v sstl135, sstl135_r v ref ? 0.575 v ref +0.575 v ref 0.675 sstl, 1.5v sstl15, sstl15_r v ref ?0.65 v ref +0.65 v ref 0.75 sstl, class i and ii, 1.8v sstl18_i, sstl18_ii v ref ?0.8 v ref +0.8 v ref 0.90 pod10, 1.0v pod10 v ref ?0.6 v ref +0.6 v ref 0.70 pod12, 1.2v pod12 v ref ?0.74 v ref +0.74 v ref 0.84 diff_hstl, class i, 1.2v diff_hstl_i_12 0.6 ? 0.125 0.6 + 0.125 0 (6) ? diff_hstl, class i and ii,1.5v diff_hstl_i, diff_hstl_ii 0.75 ? 0.125 0.75 + 0.125 0 (6) ? diff_hstl, class i and ii, 1.8v diff_hstl_i_18, diff_hstl_ii_18 0.9 ? 0.125 0.9 + 0.125 0 (6) ? diff_hsul, 1.2v diff_hsul_12 0.6 ? 0.125 0.6 + 0.125 0 (6) ? diff_sstl, 1.2v diff_sstl12 0.6 ? 0.125 0.6 + 0.125 0 (6) ? diff_sstl135/diff_sstl135_r, 1.35v diff_sstl135, diff_sstl135_r 0.675 ? 0.125 0.675 + 0.125 0 (6) ? diff_sstl15/diff_sstl15_r, 1.5v diff_sstl15, diff_sstl15_r 0.75 ? 0.125 0.75 + 0.125 0 (6) ? diff_sstl18_i/diff_sstl18_ii, 1.8v diff_sstl18_i, diff_sstl18_ii 0.9 ? 0.125 0.9 + 0.125 0 (6) ? diff_pod10, 1.0v diff_pod10 0.70 ? 0.125 0.70 + 0.125 0 (6) ? diff_pod12, 1.2v diff_pod12 0.84 ? 0.125 0.84 + 0.125 0 (6) ? lvds (low-voltage differential signaling), 1.8v lvds 0.9 ? 0.125 0.9 + 0.125 0 (6) ? lvds_25, 2.5v lvds_25 1.25 ? 0.125 1.25 + 0.125 0 (6) ? sub_lvds, 1.8v sub_lvds 0.9 ? 0.125 0.9 + 0.125 0 (6) ? slvs, 1.8v slvs_400_18 0.9 ? 0.125 0.9 + 0.125 0 (6) ? slvs, 2.5v slvs_400_25 1.25 ? 0.125 1.25 + 0.125 0 (6) ? lvpecl, 2.5 lvpecl 1.25 ? 0.125 1.25 + 0.125 0 (6) ? blvds_25, 2.5v blvds_25 1.25 ? 0.125 1.25 + 0.125 0 (6) ? mini_lvds_25, 2.5v mini_lvds_25 1.25 ? 0.125 1.25 + 0.125 0 (6) ? ppds_25 ppds_25 1.25 ? 0.125 1.25 + 0.125 0 (6) ? rsds_25 rsds_25 1.25 ? 0.125 1.25 + 0.125 0 (6) ? tmds_33 tmds_33 3 ? 0.125 3 + 0.125 0 (6) ? notes: 1. the input delay measuremen t methodology parameters for lvdci are th e same for lvcmos standards of the same voltage. input delay measurement method ology parameters for hslvdci are the same as for hstl_ii standards of the same voltage. parameters for all other dci standards are the same for the corresponding non-dci standards. 2. input waveform switches between v l and v h . 3. measurements are made at typical, minimum, and maximum v ref values. reported delays reflect worst case of these measurements. v ref values listed are typical. 4. input voltage level from which measurement starts. 5. this is an input voltage referenc e that bears no relation to the v ref /v meas parameters found in ibis models and/or noted in figure 1 . 6. the value given is the differential input voltage. table 30: input delay measurement methodology (cont?d) description i/o standard attribute v l (1)(2) v h (1)(2) v meas (1)(4)(6) v ref (1)(3)(5) s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 33 output delay measurements output delays are measured with short output traces . standard termination was used for all testing. the propagation delay of the trace is characterized separa tely and subtracted from the final measurement, and is therefore not included in the generalized test setups shown in figure 1 and figure 2 . parameters v ref , r ref , c ref , and v meas fully describe the test conditions for each i/o standard. the most accurate prediction of propagat ion delay in any given application can be obtained through ibis simulation, using this method: 1. simulate the output driver of choice into the generalized test setup using values from table 31 . 2. record the time to v meas . 3. simulate the output driver of choice into the ac tual pcb trace and load using the appropriate ibis model or capacitance value to represent the load. 4. record the time to v meas . 5. compare the results of step 2 and step 4 . the increase or decrease in delay yields the actual propagation delay of the pcb trace. x-ref target - figure 1 figure 1: single-ended test setup x-ref target - figure 2 figure 2: differential test setup v ref r ref v meas (voltage level when taking delay measurement) c ref (probe capacitance) fpga output ds892_01_120414 r ref v meas + ? c ref fpga output ds892_02_120414 s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 34 table 31: output delay measurement methodology description i/o standard attribute r ref ( ) c ref (1) (pf) v meas (v) v ref (v) lvcmos, 1.2v lvcmos12 1m 0 0.6 0 lvcmos 1.5v lvcmos15 1m 0 0.75 0 lvcmos 1.8v lvcmos18 1m 0 0.9 0 lvcmos, 2.5v lvcmos25 1m 0 1.25 0 lvcmos, 3.3v lvcmos33 1m 0 1.65 0 lvttl, 3.3v lvttl 1m 0 1.65 0 lvdci/hslvdci, 1.5v lvdci_15, hslvdci_15 50 0 v ref 0.75 lvdci/hslvdci, 1.8v lvdci_18, hslvdci_18 50 0 v ref 0.9 hstl (high-speed transceiver logic), class i, 1.2v hstl_i_12 50 0 v ref 0.6 hstl, class i, 1.5v hstl_i 50 0 v ref 0.75 hstl, class ii, 1.5v hstl_ii 25 0 v ref 0.75 hstl, class i, 1.8v hstl_i_18 50 0 v ref 0.9 hstl, class ii, 1.8v hstl_ii_18 25 0 v ref 0.9 hsul (high-speed unterminated logic), 1.2v hsul_12 50 0 v ref 0.6 sstl12, 1.2v sstl12 50 0 v ref 0.6 sstl135/sstl135_r, 1.35v sstl135, sstl135_r 50 0 v ref 0.675 sstl15/sstl15_r, 1.5v sstl15, sstl15_r 50 0 v ref 0.75 sstl (stub series terminated logic), class i and class ii, 1.8v sstl18_i, sstl18_ii 50 0 v ref 0.9 pod10, 1.0v pod10 50 0 v ref 1.0 pod12, 1.2v pod12 50 0 v ref 1.2 diff_hstl, class i, 1.2v diff_hstl_i_12 50 0 v ref 0.6 diff_hstl, class i and ii, 1.5v diff_hstl_i, diff_hstl_ii 50 0 v ref 0.75 diff_hstl, class i and ii, 1.8v diff_hstl_i_18, diff_hstl_ii_18 50 0 v ref 0.9 diff_hsul_12, 1.2v diff_hsul_12 50 0 v ref 0.6 diff_sstl12, 1.2v diff_sstl12 50 0 v ref 0.6 diff_sstl135/diff_sstl135_r, 1.35v diff_sstl135, diff_sstl135_r 50 0 v ref 0.675 diff_sstl15/diff_sstl15_r, 1.5v diff_sstl15, diff_sstl15_r 50 0 v ref 0.75 diff_sstl18, class i and ii, 1.8v diff_sstl18_i, diff_sstl18_ii 50 0 v ref 0.9 diff_pod10, 1.0v diff_pod10 50 0 v ref 1.0 diff_pod12, 1.2v diff_pod12 50 0 v ref 1.2 lvds (low-voltage differential signaling), 1.8v lvds 100 0 0 (2) 0 lvds, 2.5v lvds_25 100 0 0 (2) 0 blvds (bus lvds), 2.5v blvds_25 100 0 0 (2) 0 mini lvds, 2.5v mini_lvds_25 100 0 0 (2) 0 ppds_25 ppds_25 100 0 0 (2) 0 rsds_25 rsds_25 100 0 0 (2) 0 s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 35 block ram and fifo switching characteristics sub_lvds sub_lvds 100 0 0 (2) 0 tmds_33 tmds_33 50 0 0 (2) 3.3 notes: 1. c ref is the capacitance of the probe, nominally 0 pf. 2. the value given is the differential output voltage. table 32: block ram and fifo switching characteristics symbol description speed grade and v ccint operating voltages units 1.0v 0.95v 0.90v -3 -2 -1/-1l -1l maximum frequency f max_wf_nc block ram (write first and no change modes) 660 585 525 525 mhz f max_rf block ram (read first mode) 575 510 460 400 mhz f max_fifo fifo in all modes without ecc 660 585 525 525 mhz f max_ecc block ram and fifo in ecc configuration without pipeline 530 450 390 390 mhz block ram and fifo in ecc configuration with pipeline and block ram in write first or no change mode. 660 585 525 525 mhz block ram in ecc configuration in read first mode with pipeline 575 510 460 400 mhz f max_addren_rdaddrchange block ram with address enable and read address change compare turned on. 575 510 460 400 mhz t pw_wf_nc (1) block ram in write_first and no_change modes and fifo. clock high/low pulse width 758 855 952 952 ps, min t pw_rf (1) block ram in read_first modes. clock high/low pulse width 870 980 1087 1250 ps, min block ram and fifo clock-to-out delays t rcko_do clock clk to dout output (without output register) 1.13 1.44 1.64 1.64 ns, max t rcko_do_reg clock clk to dout output (with output register) 0.37 0.44 0.49 0.49 ns, max notes: 1. the mmcm and pll duty_cycle attribute should be set to 50% to meet the pulse width requirements at the higher frequencies. table 31: output delay measur ement methodology (cont?d) description i/o standard attribute r ref ( ) c ref (1) (pf) v meas (v) v ref (v) s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 36 input/output delay switching characteristics dsp48 slice switching characteristics table 33: input/output delay switching characteristics symbol description speed grade and v ccint operating voltages units 1.0v 0.95v 0.90v -3 -2 -1/-1l -1l f refclk refclk frequency (component mode) 200 to 800 mhz refclk frequency (native mode) 200 to 2400 200 to 2400 200 to 2133 200 to 2133 mhz t minper_rst minimum reset pulse width 52.00 ns t idelay_resolution / t odelay_resolution idelay/odelay chain resolution 2.5 to 15 ps table 34: dsp48 slice switching characteristics symbol description speed grade and v ccint operating voltages units 1.0v 0.95v 0.90v -3 -2 -1/-1l -1l maximum frequency f max with all registers used 741 661 594 594 mhz f max_patdet with pattern detector 687 581 512 512 mhz f max_mult_nomreg two register multiply without mreg 462 429 361 361 mhz f max_mult_nomreg_patdet two register multiply without mreg with pattern detect 428 387 326 326 mhz f max_preadd_noadreg without adreg 468 429 358 358 mhz f max_nopipelinereg without pipeline registers (mreg, adreg) 335 312 260 260 mhz f max_nopipelinereg_patdet without pipeline registers (mreg, adreg) with pattern detect 316 286 238 238 mhz s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 37 clock buffers and networks table 35: clock buffers switching characteristics symbol description speed grade and v ccint operating voltages units 1.0v 0.95v 0.90v -3 -2 -1/-1l -1l global clock switching characte ristics (including bufgctrl) f max maximum frequency of a global clock tree (bufg) 850 725 630 630 mhz global clock buffer with input divide capability (bufgce_div) f max maximum frequency of a global clock buffer with input divide capability (bufgce_div) 850 725 630 630 mhz global clock buffer with clock enable (bufgce) f max maximum frequency of a global clock buffer with clock enable (bufgce) 850 725 630 630 mhz leaf clock buffer with clock enable (bufce_leaf) f max maximum frequency of a leaf clock buffer with clock enable (bufce_leaf) 850 725 630 630 mhz gth/gty clock buffer with clock enable an d clock input divide capability (bufg_gt) f max maximum frequency of a serial transceiver clock buffer with clock enable and clock input divide capability 512 512 512 512 mhz s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 38 mmcm switching characteristics table 36: mmcm specification symbol description speed grade and v ccint operating voltages units 1.0v 0.95v 0.90v -3 -2 -1/-1l -1l mmcm_f inmax maximum input clock frequency 1066 933 800 800 mhz mmcm_f inmin minimum input clock frequency 10 10 10 10 mhz mmcm_f injitter maximum input clock period jitter < 20% of clock input period or 1 ns max mmcm_f induty input duty cycle range: 10?49 mhz 25?75 % input duty cycle range: 50?199 mhz 30?70 % input duty cycle range: 200?399 mhz 35?65 % input duty cycle range: 400?499 mhz 40?60 % input duty cycle range: >500 mhz 45?55 % mmcm_f min_psclk minimum dynamic phase shift clock frequency 0.01 0.01 0.01 0.01 mhz mmcm_f max_psclk maximum dynamic phase shift clock frequency 550 500 450 450 mhz mmcm_f vcomin minimum mmcm vco frequency 600 600 600 600 mhz mmcm_f vcomax maximum mmcm vco frequency 1600 1440 1200 1200 mhz mmcm_f bandwidth low mmcm bandwidth at typical (1) 1.00 1.00 1.00 1.00 mhz high mmcm bandwidth at typical (1) 4.00 4.00 4.00 4.00 mhz mmcm_t statphaoffset static phase offset of the mmcm outputs (2) 0.12 0.12 0.12 0.12 ns mmcm_t outjitter mmcm output jitter note 3 mmcm_t outduty mmcm output clock duty cycle precision (4) 0.165 0.20 0.20 0.20 ns mmcm_t lockmax mmcm maximum lock time for mmcm_f pfdmin frequencies above 20 mhz 100 100 100 100 s mmcm maximum lock time for mmcm_f pfdmin frequencies from 10 mhz to 20 mhz 200 200 200 200 s mmcm_f outmax mmcm maximum output frequency 850 725 630 630 mhz mmcm_f outmin mmcm minimum output frequency (4)(5) 4.69 4.69 4.69 4.69 mhz mmcm_t extfdvar external clock feedback variation < 20% of clock input period or 1 ns max mmcm_rst minpulse minimum reset pulse width 5.00 5.00 5.00 5.00 ns mmcm_f pfdmax maximum frequency at the phase frequency detector 550 500 450 450 mhz mmcm_f pfdmin minimum frequency at the phase frequency detector 10 10 10 10 mhz mmcm_t fbdelay maximum delay in the feedback path 5 ns max or one clock cycle notes: 1. the mmcm does not filter typical spread-spectrum input cloc ks because they are usually far below the bandwidth filter frequencies. 2. the static offset is measured between any mmcm outputs with identical phase. 3. values for this parameter are av ailable in the clocking wizard. 4. includes global clock buffer. 5. calculated as f vco /128 assuming output duty cycle is 50%. s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 39 pll switching characteristics table 37: pll specification (1) symbol description speed grade and v ccint operating voltages units 1.0v 0.95v 0.90v -3 -2 -1/-1l -1l pll_f inmax maximum input clock frequency 1066 933 800 800 mhz pll_f inmin minimum input clock frequency 70707070mhz pll_f injitter maximum input clock period jitter < 20% of clock input period or 1 ns max pll_f induty input duty cycle range: 70?399 mhz 35?65 % input duty cycle range: 400?499 mhz 40?60 % input duty cycle range: >500 mhz 45?55 % pll_f vcomin minimum pll vco frequency 600 600 600 600 mhz pll_f vcomax maximum pll vco frequency 1335 1335 1200 1200 mhz pll_t statphaoffset static phase offset of the pll outputs (2) 0.12 0.12 0.12 0.12 ns pll_t outjitter pll output jitter note 3 pll_t outduty pll clkout0/clkout0b/clkout1/clkout1b duty-cycle precision (4) 0.1650.200.200.20 ns pll_t lockmax pll maximum lock time 100 s pll_f outmax pll maximum output frequency at clkout0/clkout0b/clkout1/clkout1b 850 725 630 630 mhz pll maximum output frequency at clkoutphy 2670 2670 2400 2400 mhz pll_f outmin pll minimum output frequency at clkout0/clkout0b/clkout1/clkout1b (5) 4.69 4.69 4.69 4.69 mhz pll minimum output frequency at clkoutphy 2 x vco mode: 1200 1 x vco mode: 600 0.5 x vco mode: 300 mhz pll_rst minpulse minimum reset pulse width 5.005.005.005.00 ns pll_f pfdmax maximum frequency at the phase frequency detector 667.5 667.5 600 600 mhz pll_f pfdmin minimum frequency at the phase frequency detector 70 70 70 70 mhz pll_f bandwidth pll bandwidth at typical 15151515mhz notes: 1. the pll does not filter typical spread-s pectrum input clocks because they are usua lly far below the loop filter frequencies. 2. the static offset is measured betwee n any pll outputs with identical phase. 3. values for this parameter are av ailable in the clocking wizard. 4. includes global clock buffer. 5. calculated as f vco /128 assuming output duty cycle is 50%. s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 40 device pin-to-pin output parameter guidelines the pin-to-pin numbers in table 38 through table 41 are based on the clock root placement in the center of the device. the actual pin-to-pin values will vary if the root placement selected is different. consult the vivado design suite timing report for the actual pin-to-pin values. table 38: global clock input to output delay without mmcm/pll (near clock region) symbol description device speed grade and v ccint operating voltages units 1.0v 0.95v 0.90v -3 -2 -1 -1l -1l sstl15 global clock input to output delay using output flip-flop, fast slew rate, without mmcm/pll. t ickof global clock input and output flip-flop without mmcm/pll (near clock region) xcku025 n/a 6.07 7.00 n/a n/a ns xcku0355.406.217.057.057.44 ns xcku0405.406.217.057.057.44 ns xcku0605.195.996.936.937.19 ns xcku0855.206.087.087.087.19 ns xcku095 n/a 6.09 7.13 n/a n/a ns xcku1155.206.087.087.087.19 ns notes: 1. this table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible i/o and clb flip-flops are clocked by the global clock net in a single slr. table 39: global clock input to output delay without mmcm/pll (far clock region) symbol description device speed grade and v ccint operating voltages units 1.0v 0.95v 0.90v -3 -2 -1 -1l -1l sstl15 global clock input to output delay using output flip-flop, fast slew rate, without mmcm/pll. t ickof_far global clock input and output flip-flop without mmcm/pll (far clock region) xcku025 n/a 6.40 7.37 n/a n/a ns xcku035 5.84 6.73 7.64 7.64 8.09 ns xcku040 5.84 6.73 7.64 7.64 8.09 ns xcku060 5.94 6.84 7.91 7.91 8.22 ns xcku085 5.95 6.98 8.12 8.12 8.21 ns xcku095 n/a 6.67 7.69 n/a n/a ns xcku115 5.95 6.98 8.12 8.12 8.21 ns notes: 1. this table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible i/o and clb flip-flops are clocked by the global clock net in a single slr. s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 41 table 40: global clock input to output delay with mmcm symbol description device speed grade and v ccint operating voltages units 1.0v 0.95v 0.90v -3 -2 -1 -1l -1l sstl15 global clock input to ou tput delay using output flip-flo p, fast slew rate, with mmcm. t ickofmmcmcc global clock input and output flip-flop with mmcm xcku025 n/a 1.80 1.88 n/a n/a ns xcku035 2.13 2.45 2.78 2.78 3.72 ns xcku040 2.13 2.45 2.78 2.78 3.72 ns xcku060 1.58 1.92 2.05 2.05 2.41 ns xcku085 1.58 1.95 2.12 2.12 2.41 ns xcku095 n/a 1.59 1.85 n/a n/a ns xcku115 1.58 1.95 2.12 2.12 2.41 ns notes: 1. this table lists representative values where one global clock input drives one vertical clock li ne in each accessible column, and where all accessible i/o and clb flip-flops are clocked by the global clock net in a single slr. 2. mmcm output jitter is already included in the timing calculation. table 41: global clock input to output delay with pll symbol description device speed grade and v ccint operating voltages units 1.0v 0.95v 0.90v -3 -2 -1 -1l -1l sstl15 global clock input to ou tput delay using output flip-flo p, fast slew rate, with pll. t ickof_pll_cc global clock input and output flip-flop with pll xcku025 n/a 5.39 6.11 n/a n/a ns xcku035 4.25 4.46 5.08 5.08 5.46 ns xcku040 4.25 4.46 5.08 5.08 5.46 ns xcku060 5.13 5.83 6.66 6.66 6.95 ns xcku085 5.14 5.96 6.85 6.85 6.96 ns xcku095 n/a 5.70 6.49 n/a n/a ns xcku115 5.14 5.96 6.85 6.85 6.96 ns notes: 1. this table lists representative values where one global clock input drives one vertic al clock line in each accessible column, and where all accessible i/o and clb flip-flops are clocked by the global clock net in a single slr. 2. pll output jitter is already included in the timing calculation. s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 42 device pin-to-pin input parameter guidelines the pin-to-pin numbers in table 42 through table 43 are based on the clock root placement in the center of the device. the actual pin-to-pin values will vary if the root placement selected is different. consult the vivado design suite timing report for the actual pin-to-pin values. table 42: global clock input setup and hold with mmcm symbol description device speed grade and v ccint operating voltages units 1.0v 0.95v 0.90v -3 -2 -1 -1l -1l input setup and hold time relative to global clock input signal using sstl15 standard. (1)(2)(3) t psmmcmcc_ku025 global clock input and input flip-flop (or latch) with mmcm setup xcku025 n/a 2.16 2.51 n/a n/a ns t phmmcmcc_ku025 hold n/a ?0.48 ?0.48 n/a n/a ns t psmmcmcc_ku035 setup xcku035 1.70 1.72 1.74 1.74 2.07 ns t phmmcmcc_ku035 hold ?0.23 ?0.23 ?0.23 ?0.23 ?0.13 ns t psmmcmcc_ku040 setup xcku040 1.70 1.72 1.74 1.74 2.07 ns t phmmcmcc_ku040 hold ?0.23 ?0.23 ?0.23 ?0.23 ?0.13 ns t psmmcmcc_ku060 setup xcku060 2.21 2.23 2.51 2.51 2.55 ns t phmmcmcc_ku060 hold ?0.47 ?0.47 ?0.47 ?0.47 ?0.15 ns t psmmcmcc_ku085 setup xcku085 2.21 2.23 2.51 2.51 2.55 ns t phmmcmcc_ku085 hold ?0.37 ?0.37 ?0.37 ?0.37 ?0.15 ns t psmmcmcc_ku095 setup xcku095 n/a 2.25 2.55 n/a n/a ns t phmmcmcc_ku095 hold n/a ?0.47 ?0.47 n/a n/a ns t psmmcmcc_ku115 setup xcku115 2.21 2.23 2.51 2.51 2.55 ns t phmmcmcc_ku115 hold ?0.37 ?0.37 ?0.37 ?0.37 ?0.15 ns notes: 1. setup and hold times are measured over worst case conditions (process, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest proc ess, slowest temperature, and sl owest voltage. hold time is measured relative to the glob al clock input signal using the fastest proces s, fastest temperature, and fastest voltage. 2. this table lists representative values wh ere one global clock input drives one vertic al clock line in each accessible column, and where all accessible i/o and clb flip-flops are clocked by the global clock net in a single slr. 3. use ibis to determine any duty-cycle di stortion incurred using various standards. s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 43 table 43: global clock input setu p and hold with pll symbol description device speed grade and v ccint operating voltages units 1.0v 0.95v 0.90v -3 -2 -1 -1l -1l input setup and hold time relative to global clock input signal using sstl15 standard. (1)(2)(3) t pspllcc_ku025 global clock input and input flip-flop (or latch) with pll setup xcku025 n/a ?0.48 ?0.48 n/a n/a ns t phpllcc_ku025 hold n/a 2.42 2.70 n/a n/a ns t pspllcc_ku035 setup xcku035 0.00 0.00 0.00 0.00 0.00 ns t phpllcc_ku035 hold 1.36 1.59 1.79 1.79 1.79 ns t pspllcc_ku040 setup xcku040 0.00 0.00 0.00 0.00 0.00 ns t phpllcc_ku040 hold 1.36 1.59 1.79 1.79 1.79 ns t pspllcc_ku060 setup xcku060 ?0.70 ?0.70 ?0.70 ?0.70 ?0.78 ns t phpllcc_ku060 hold 2.18 2.41 2.75 2.75 2.98 ns t pspllcc_ku085 setup xcku085 ?0.66 ?0.66 ?0.66 ?0.66 ?0.78 ns t phpllcc_ku085 hold 2.18 2.46 2.83 2.83 2.98 ns t pspllcc_ku095 setup xcku095 n/a ?0.94 ?0.94 n/a n/a ns t phpllcc_ku095 hold n/a 2.36 2.71 n/a n/a ns t pspllcc_ku115 setup xcku115 ?0.66 ?0.66 ?0.66 ?0.66 ?0.78 ns t phpllcc_ku115 hold 2.18 2.46 2.83 2.83 2.98 ns notes: 1. setup and hold times are measured over worst case conditio ns (process, voltage, temperat ure). setup time is measured relative to the global clock input signal using the slowest process, slowest temperat ure, and slowest voltage. hold time is measured relative to the glob al clock input signal using the fastest proces s, fastest temperature, and fastest voltage. 2. this table lists representative values where one global clock in put drives one vertical clock line in each accessible column, and where all accessible i/o and clb flip-flops are clocked by the global clock net in a single slr. 3. use ibis to determine any duty-cycle di stortion incurred using various standards. table 44: sampling window description speed grade and v ccint operating voltages units 1.0v 0.95v 0.90v -3 -2e -2i -1 -1l -1l t samp_bufg (1) 510 560 610 610 610 610 ps t samp_native_dpa 100 100 100 125 125 150 ps t samp_native_bisc 60 60 60 85 85 110 ps notes: 1. this parameter indicates the total sampling error of the ki ntex ultrascale fpgas ddr inpu t registers, measured across voltage, temperature, and process. the characterization methodology uses the mmcm to capture the ddr input registers? edges of operation. these measurements include: clk0 mmcm jitter, mmcm accuracy (phase offset), and mmcm phase shift resolution. these measurements do not include package or clock tree skew. s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 44 package parameter guidelines the parameters in this section provide the necessary values for calculating timing budgets for clock transmitter and receiver data-valid windows. table 45: package skew symbol description device package value units pkgskew package skew xcku025 ffva1156 162 ps xcku035 fbva676 173 ps sfva784 134 ps fbva900 184 ps ffva1156 168 ps xcku040 fbva676 173 ps sfva784 134 ps fbva900 184 ps ffva1156 168 ps xcku060 ffva1156 168 ps ffva1517 169 ps xcku085 flva1517 217 ps flvb1760 175 ps flvf1924 143 ps xcku095 ffva1156 162 ps ffvc1517 181 ps ffvb1760 128 ps ffvb2104 191 ps xcku115 flva1517 217 ps flvd1517 143 ps flvb1760 177 ps flvd1924 172 ps flvf1924 143 ps flva2104 184 ps flvb2104 198 ps notes: 1. these values represent the worst-case skew between any two se lectio resources in the packag e: shortest delay to longest delay from die pad to ball. 2. package delay information is available for these device/package combinations. this information can be used to deskew the package. s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 45 gth transceiver specifications gth transceiver dc input and output levels table 46 summarizes the dc specifications of the gth transc eivers in kintex ultrasca le fpgas. consult the ultrascale architecture gt h transceiver user guide ( ug576 ) for further details. table 46: gth transceiver dc specifications symbol dc parameter conditions min typ max units dv ppin differential peak-to-peak input voltage (external ac coupled) >10.3125 gb/s 150 ? 1250 mv 6.6 gb/s to 10.3125 gb/s 150 ? 1250 mv 6.6 gb/s 150 ? 2000 mv v in single-ended input voltage. voltage measured at the pin referenced to gnd. dc coupled v mgtavtt =1.2v ?400 ? v mgtavtt mv v cmin common mode input voltage dc coupled v mgtavtt =1.2v ?2/3v mgtavtt ?mv d vppout differential peak-to-peak output voltage (1) transmitter output swing is set to 1100 800 ? ? mv v cmoutdc common mode output voltage: dc coupled (equation based) when remote rx is terminated to gnd v mgtavtt /2 ? d vppout /4 mv when remote rx termination is floating v mgtavtt ? d vppout /2 mv when remote rx is terminated to v rx_term (2) mv v cmoutac common mode output voltage: ac coupled (equation based) v mgtavtt ? d vppout /2 mv r in differential input resistance ? 100 ? r out differential output resistance ? 100 ? t oskew transmitter output pair (txp and txn) intra-pair skew (all packages) ??10ps c ext recommended external ac coupling capacitor (3) ? 100 ? nf notes: 1. the output swing and pre-emphas is levels are programmable using the attributes discussed in the ultrascale architecture gth transceiver user guide ( ug576 ), and can result in values lowe r than reported in this table. 2. v rx_term is the remote rx termination voltage. 3. other values can be used as appropriate to conform to specific protocols and standards. v mgtavtt d vppout 4 ----------------------- - ? v mgtavtt v rx_term ? 2 ------------------------------------------------------- - ?? ?? ? s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 46 table 47 and table 48 summarize the dc specifications of the gt h transceivers input and output clocks in kintex ultrascale fpgas. consult the ultrascale architecture gth transceiver user guide ( ug576 ) for further details. x-ref target - figure 3 figure 3: single-ended peak-to-peak voltage x-ref target - figure 4 figure 4: differential peak-to-peak voltage table 47: gth transceiver clock dc input level specification symbol dc parameter min typ max units v idiff differential peak-to-peak input voltage 250 ? 2000 mv r in differential input resistance ? 100 ? c ext required external ac coupling capacitor ? 10 ? nf table 48: gth transceiver clock outp ut level specification symbol description conditions min typ max units v ol output high voltage for p and n r t = 100 across p and n signals ? 400 ? mv v oh output low voltage for p and n r t = 100 across p and n signals ? 760 ? mv v ddout d if fe rential outp ut voltage ( p ? n ) , p = h i g h (n?p), n = high r t = 100 across p and n signals ? 360 ? mv v cmout common mode voltage r t = 100 across p and n signals ? 580 ? mv 0 +v p n ds892_03_ 120414 single-ended peak-to-peak voltage 0 +v ?v p?n ds892_04_ 120414 differential peak-to-peak voltage differential peak-to-peak voltage = (single-ended peak-to-peak voltage) x 2 s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 47 gth transceiver switching characteristics consult the ultrascale architecture gt h transceiver user guide ( ug576 ) for further information. table 49: gth transceiver performance symbol description output divider speed grade, temp erature ranges, and v ccint operating voltages units 1.0v 0.95v 0.90v -3e -2e, -2i -1c,-1i,-1li -1li package type ff/fl fb ff/fl fb all packages all packages f gthmax gth maximum line rate 16.375 12.5 16.375 12.5 12.5 12.5 (1) gb/s f gthmin gth minimum line rate 0.5 0.5 0.5 0.5 0.5 0.5 gb/s min max min max min max min max f gthcrange cpll line rate range (2) 1 4.0 12.5 4.0 12.5 4.0 8.5 4.0 8.5 gb/s 2 2.0 6.25 2.0 6.25 2.0 4.25 2.0 4.25 gb/s 4 1.0 3.125 1.0 3.125 1.0 2.125 1.0 2.125 gb/s 8 0.5 1.5625 0.5 1.5625 0.5 1.0625 0.5 1.0625 gb/s 16 n/a gb/s min max min max min max min max f gthqrange1 qpll0 line rate range (3) 1 9.8 16.375 9.8 16.375 9.8 12.5 9.8 12.5 gb/s 2 4.9 8.1875 4.9 8.1875 4.9 8.1875 4.9 8.1875 gb/s 4 2.45 4.0938 2.45 4.0938 2.45 4.0938 2.45 4.0938 gb/s 8 1.225 2.0469 1.225 2.0469 1.225 2.0469 1.225 2.0469 gb/s 16 0.6125 1.0234 0.6125 1.0234 0.6125 1.0234 0.6125 1.0234 gb/s min max min max min max min max f gthqrange2 qpll1 line rate range (4) 1 8.0 13.0 8.0 13.0 8.0 12.5 8.0 12.5 gb/s 2 4.0 6.5 4.0 6.5 4.0 6.5 4.0 6.5 gb/s 4 2.0 3.25 2.0 3.25 2.0 3.25 2.0 3.25 gb/s 8 1.0 1.625 1.0 1.625 1.0 1.625 1.0 1.625 gb/s 16 0.5 0.8125 0.5 0.8125 0.5 0.8125 0.5 0.8125 gb/s min max min max min max min max f cpllrange cpll frequency range 2.0 6.25 2.0 6.25 2.0 4.25 2.0 4.25 ghz f qpll0range qpll0 frequency range 9.8 16.375 9.8 16.375 9.8 16.375 9.8 16.375 ghz f qpll1range qpll1 frequency range 8.0 13.0 8.0 13.0 8.0 13.0 8.0 13.0 ghz notes: 1. designs must use vivado design suit e v2015.4.1 or later to achieve 12.5 gb/s. 2. the values listed are the rounded results of the calculated equation (2 x cpll_frequency)/output_divider. 3. the values listed are the rounded results of the ca lculated equation (qpll0_frequency)/output_divider. 4. the values listed are the rounded results of the ca lculated equation (qpll1_frequency)/output_divider. table 50: gth transceiver dynamic reconfiguration port (drp) switching characteristics symbol description all devices units f gthdrpclk gthdrpclk maximum frequency 250 mhz s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 48 table 51: gth transceiver reference cloc k switching characteristics symbol description conditions min typ max units f gclk reference clock frequency range 60 ? 820 mhz t rclk reference clock rise time 20% ? 80% ? 200 ? ps t fclk reference clock fall time 80% ? 20% ? 200 ? ps t dcref reference clock duty cycle transceiver pll only 40 50 60 % x-ref target - figure 5 figure 5: reference clock timing parameters table 52: gth transceiver reference clock os cillator selection phase noise mask symbol description offset frequency min typ max units qpll refclkmask (1)(2) qpll0/qpll1 reference clock select phase noise mask at refclk frequency = 312.5 mhz. 10 khz ? ? ?105 dbc/hz 100 khz ? ? ?124 1 mhz ? ? ?130 cpll refclkmask (1)(2) cpll reference clock select phase noise mask at refclk frequency = 312.5 mhz. 10 khz ? ? ?105 dbc/hz 100 khz ? ? ?124 1 mhz ? ? ?130 50 mhz ? ? ?140 notes: 1. for reference clock frequencies other than 312.5 mhz, adjust the ph ase-noise mask values by 20 x log(n/312.5) where n is the new reference clock frequency in mhz. 2. this reference clock phase-noise mask is superseded by an y reference clock phase-noise mask that is specified in a supported protocol, e.g., pcie. table 53: gth transceiver pll/lock time adaptation symbol description conditions min typ max units t lock initial pll lock ? ? 1 ms t dlock clock recovery phase acquisition and adaptation time for decision feedback equalizer (dfe). after the pll is locked to the reference clock, this is the time it takes to lock the clock data recovery (cdr) to the data present at the input. ? 50,000 37 x 10 6 ui clock recovery phase acquisition and adaptation time for low-power mode (lpm) when the dfe is disabled. ?50,0002.3x10 6 ui ds892_05_ 120414 80% 20% t fclk t rclk s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 49 table 54: gth transceiver user clock switching characteristics (1) symbol description data width conditions (bit) speed grade, temp erature ranges, and v ccint operating voltages units 1.0v 0.95v 0.90v internal logic interconnect logic -3e -2e, -2i -1c, -1i, -1li -1li f txoutpma txoutclk maximum frequency sourced from outclkpma 511.719 511.719 390.625 390.625 mhz f rxoutpma rxoutclk maximum frequency sourced from outclkpma 511.719 511.719 390.625 390.625 mhz f txoutprogdiv txoutclk maximum frequency sourced from txprogdivclk 511.719 511.719 511.719 511.719 mhz f rxoutprogdiv rxoutclk maximum frequency sourced from rxprogdivclk 511.719 511.719 511.719 511.719 mhz f txin txusrclk maximum frequency 16 16, 32 511.719 511.719 390.625 390.625 mhz 32 32, 64 511.719 511.719 390.625 390.625 mhz 20 20, 40 409.375 409.375 312.500 312.500 mhz 40 40, 80 409.375 409.375 312.500 312.500 mhz f rxin rxusrclk maximum frequency 16 16, 32 511.719 511.719 390.625 390.625 mhz 32 32, 64 511.719 511.719 390.625 390.625 mhz 20 20, 40 409.375 409.375 312.500 312.500 mhz 40 40, 80 409.375 409.375 312.500 312.500 mhz f txin2 txusrclk2 maximum frequency 16 16 511.719 511.719 390.625 390.625 mhz 16, 32 32 511.719 511.719 390.625 390.625 mhz 32 64 255.860 255.860 195.313 195.313 mhz 20 20 409.375 409.375 312.500 312.500 mhz 20, 40 40 409.375 409.375 312.500 312.500 mhz 40 80 204.688 204.688 156.250 156.250 mhz f rxin2 rxusrclk2 maximum frequency 16 16 511.719 511.719 390.625 390.625 mhz 16, 32 32 511.719 511.719 390.625 390.625 mhz 32 64 255.860 255.860 195.313 195.313 mhz 20 20 409.375 409.375 312.500 312.500 mhz 20, 40 40 409.375 409.375 312.500 312.500 mhz 40 80 204.688 204.688 156.250 156.250 mhz notes: 1. clocking must be implemented as described in ultrascale architecture gt h transceiver user guide ( ug576 ). s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 50 table 55: gth transceiver transmitter switching characteristics symbol description condition min typ max units f gthtx serial data rate range 0.500 ? f gthmax gb/s t rtx tx rise time 20%?80% ? 40 ? ps t ftx tx fall time 80%?20% ? 40 ? ps t llskew tx lane-to-lane skew (1) ??500ps v txoobvdpp electrical idle amplitude ? ? 15 mv t txoobtransition electrical idle transition time ? ? 140 ns t j16.3_qpll total jitter (2)(4) 16.3 gb/s ? ? 0.28 ui d j16.3_qpll deterministic jitter (2)(4) ? ? 0.17 ui t j15_qpll total jitter (2)(4) 15.0 gb/s ? ? 0.28 ui d j15_qpll deterministic jitter (2)(4) ? ? 0.17 ui t j14.1_qpll total jitter (2)(4) 14.1 gb/s ? ? 0.28 ui d j14.1_qpll deterministic jitter (2)(4) ? ? 0.17 ui t j14.025_qpll total jitter (2)(4) 14.025 gb/s ? ? 0.28 ui d j14.025_qpll deterministic jitter (2)(4) ? ? 0.17 ui t j13.1_qpll total jitter (2)(4) 13.1 gb/s ? ? 0.28 ui d j13.1_qpll deterministic jitter (2)(4) ? ? 0.17 ui t j12.5_qpll total jitter (2)(4) 12.5 gb/s ? ? 0.28 ui d j12.5_qpll deterministic jitter (2)(4) ? ? 0.17 ui t j12.5_cpll total jitter (3)(4) 12.5 gb/s ? ? 0.33 ui d j12.5_cpll deterministic jitter (3)(4) ? ? 0.17 ui t j11.3_qpll total jitter (2)(4) 11.3 gb/s ? ? 0.28 ui d j11.3_qpll deterministic jitter (2)(4) ? ? 0.17 ui t j10.3_qpll total jitter (2)(4) 10.3 gb/s ? ? 0.28 ui d j10.3_qpll deterministic jitter (2)(4) ? ? 0.17 ui t j10.3_cpll total jitter (3)(4) 10.3 gb/s ? ? 0.33 ui d j10.3_cpll deterministic jitter (3)(4) ? ? 0.17 ui t j9.8_qpll total jitter (2)(4) 9.8 gb/s ? ? 0.28 ui d j9.8_qpll deterministic jitter (2)(4) ? ? 0.17 ui t j9.8_cpll total jitter (3)(4) 9.8 gb/s ? ? 0.28 ui d j9.8_cpll deterministic jitter (3)(4) ? ? 0.17 ui t j8.0_cpll total jitter (3)(4) 8.0 gb/s ? ? 0.32 ui d j8.0_cpll deterministic jitter (3)(4) ? ? 0.17 ui t j6.6_cpll total jitter (3)(4) 6.6 gb/s ? ? 0.30 ui d j6.6_cpll deterministic jitter (3)(4) ? ? 0.15 ui t j5.0 total jitter (3)(4) 5.0 gb/s ? ? 0.30 ui d j5.0 deterministic jitter (3)(4) ? ? 0.15 ui t j4.25 total jitter (3)(4) 4.25 gb/s ? ? 0.30 ui d j4.25 deterministic jitter (3)(4) ? ? 0.15 ui t j4.0l total jitter (3)(4) 4.0 gb/s (5) ? ? 0.32 ui d j4.0l deterministic jitter (3)(4) ? ? 0.16 ui s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 51 t j3.2 total jitter (3)(4) 3.2 gb/s (6) ? ? 0.20 ui d j3.2 deterministic jitter (3)(4) ? ? 0.10 ui t j2.5 total jitter (3)(4) 2.5 gb/s (7) ? ? 0.20 ui d j2.5 deterministic jitter (3)(4) ? ? 0.10 ui t j1.25 total jitter (3)(4) 1.25 gb/s (8) ? ? 0.15 ui d j1.25 deterministic jitter (3)(4) ? ? 0.06 ui t j500 total jitter (3)(4) 500 mb/s (9) ? ? 0.10 ui d j500 deterministic jitter (3)(4) ? ? 0.03 ui notes: 1. using same refclk input with tx phase alignment enabled for up to four fully po pulated gth quads at maximum line rate. 2. using qpll_fbdiv = 40, 40-bit internal data width. these va lues are not intended for pr otocol specific compliance determinations. 3. using cpll_fbdiv = 2, 40-bit internal da ta width. these values are not intend ed for protocol specific compliance determinations. 4. all jitter values are based on a bit-error ratio of 10 -12 . 5. cpll frequency at 2.0 ghz and txout_div = 1 6. cpll frequency at 3.2 ghz and txout_div = 2. 7. cpll frequency at 2.5 ghz and txout_div = 2. 8. cpll frequency at 2.5 ghz and txout_div = 4. 9. cpll frequency at 2.0 ghz and txout_div = 4. table 56: gth transceiver receiver switching characteristics symbol description condition min typ max units f gthrx serial data rate 0.500 ? f gthmax gb/s t rxelecidle time for rxelecidle to respond to loss or restoration of data ?10?ns r xoobvdpp oob detect threshold peak-to-peak 60 ? 150 mv r xsst receiver spread-spectrum tracking (1) modulated at 33 khz ?5000 ? 0 ppm r xrl run length (cid) ? ? 256 ui r xppmtol data/refclk ppm offset tolerance bit rates 6.6 gb/s ?1250 ? 1250 ppm bit rates > 6.6 gb/s and 8.0 gb/s ?700 ? 700 ppm bit rates > 8.0 gb/s ?200 ? 200 ppm sj jitter tolerance (2) j t_sj16.3 sinusoidal jitter (qpll) (3) 16.3 gb/s 0.30 ? ? ui j t_sj15 sinusoidal jitter (qpll) (3) 15.0 gb/s 0.30 ? ? ui j t_sj14.1 sinusoidal jitter (qpll) (3) 14.1 gb/s 0.30 ? ? ui j t_sj13.1 sinusoidal jitter (qpll) (3) 13.1 gb/s 0.30 ? ? ui j t_sj12.5 sinusoidal jitter (qpll) (3) 12.5 gb/s 0.30 ? ? ui j t_sj11.3 sinusoidal jitter (qpll) (3) 11.3 gb/s 0.30 ? ? ui j t_sj10.3_qpll sinusoidal jitter (qpll) (3) 10.3 gb/s 0.30 ? ? ui j t_sj10.3_cpll sinusoidal jitter (cpll) (3) 10.3 gb/s 0.30 ? ? ui j t_sj9.8 sinusoidal jitter (qpll) (3) 9.8 gb/s 0.30 ? ? ui j t_sj8.0_qpll sinusoidal jitter (qpll) (3) 8.0 gb/s 0.44 ? ? ui table 55: gth transceiver transmitter switching characteristics (cont?d) symbol description condition min typ max units s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 52 j t_sj8.0_cpll sinusoidal jitter (cpll) (3) 8.0 gb/s 0.42 ? ? ui j t_sj6.6_cpll sinusoidal jitter (cpll) (3) 6.6 gb/s 0.44 ? ? ui j t_sj5.0 sinusoidal jitter (cpll) (3) 5.0 gb/s 0.44 ? ? ui j t_sj4.25 sinusoidal jitter (cpll) (3) 4.25 gb/s 0.44 ? ? ui j t_sj4.0l sinusoidal jitter (cpll) (3) 4.0 gb/s (4) 0.45 ? ? ui j t_sj3.75 sinusoidal jitter (cpll) (3) 3.75 gb/s 0.44 ? ? ui j t_sj3.2 sinusoidal jitter (cpll) (3) 3.2 gb/s (5) 0.45 ? ? ui j t_sj2.5 sinusoidal jitter (cpll) (3) 2.5 gb/s (6) 0.50 ? ? ui j t_sj1.25 sinusoidal jitter (cpll) (3) 1.25 gb/s (7) 0.50 ? ? ui j t_sj500 sinusoidal jitter (cpll) (3) 500 mb/s 0.40 ? ? ui sj jitter tolerance with stressed eye (2) j t_tjse3.2 total jitter with stressed eye (8) 3.2 gb/s 0.70 ? ? ui j t_tjse6.6 6.6 gb/s 0.70 ? ? ui j t_sjse3.2 sinusoidal jitter with stressed eye (8) 3.2 gb/s 0.10 ? ? ui j t_sjse6.6 6.6 gb/s 0.10 ? ? ui notes: 1. using rxout_div = 1, 2, and 4. 2. all jitter values are based on a bit error ratio of 10 ?12 . 3. the frequency of the injected sinusoidal jitter is 10 mhz. 4. cpll frequency at 2.0 ghz and rxout_div = 1 5. cpll frequency at 3.2 ghz and rxout_div = 2. 6. cpll frequency at 2.5 ghz and rxout_div = 2. 7. cpll frequency at 2.5 ghz and rxout_div = 4. 8. composite jitter with rx equalizer enabled. dfe disabled. table 56: gth transceiver receiver switching characteristics (cont?d) symbol description condition min typ max units s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 53 gth transceiver electrical compliance the ultrascale architecture gth transceiver user guide ( ug576 ) contains recommend ed use modes that ensure compliance for the protocols listed in table 57 . the transceiver wizard provides the recommended settings for those use cases and for protocol specific characteristics. table 57: gth transceiver protocol list protocol specification serial rate (gb/s) electrical compliance caui-10 ieee 802.3-2012 10.3125 compliant nppi ieee 802.3-2012 10.3125 compliant 10gbase-kr ieee 802.3-2012 10.3125 compliant sfp+ sff-8431 (sr and lr) 9.95328?11.10 compliant xfp inf-8077i, revision 4.5 10.3125 compliant rxaui cei-6g-sr 6.25 compliant 5.0g ethernet ieee 802.3bx (par) 5.0 compliant qsgmii qsgmii v1.2 (cisco systems, eng-46158) 5.0 compliant xaui ieee 802.3-2012 3.125 compliant 2.5g ethernet ieee 802.3bx (par) 2.5 compliant 1000base-x ieee 802.3-2012 1.25 compliant otu2 itu g.8251 10.709225 compliant otu4 (otl4.10) oif-cei-11g-sr 11.180997 compliant oc-3/12/48/192 gr-253-core 0.1555?9.956 compliant interlaken oif-cei-6g, oif-cei-11g-sr 4.25?12.5 compliant pcie gen1, 2, 3 pci express base 3.0 2.5, 5.0, and 8.0 compliant uhd-sdi (1) smpte st-2081 6g, smpte st-2082 12g 6 and 12 compliant sdi (1) smpte 424m-2006 0.27?2.97 compliant hybrid memory cube (hmc) hmc -15g-sr 12.5 and 15.0 compliant cpri cpri_v_6_1_2014-07-01 0.6144?12.165 compliant hdmi (2) hdmi 2.0 all compliant passive optical network (pon) 10g-epon, 1g-epon, ng-pon2, xg-pon, and 2.5g-pon 0.155?10.3125 compliant jesd204a/b oif-cei-6g, oif-cei-11g 3.125?12.5 compliant serial rapidio rapidio specification 3.1 1.25?10.3125 compliant displayport (source only) dp 1.2b cts 1.62?5.4 compliant fibre channel fc-pi-4 1.0625?14.025 compliant sata gen1, 2, 3 serial ata revision 3.0 specification 1.5, 3.0, and 6.0 compliant sas gen1, 2, 3 t10/bsr incits 519 3.0, 6.0, and 12.0 compliant sfi-5 oif-sfi5-01.0 0.625?12.5 compliant notes: 1. sdi protocols require external circuitry to achieve compliance. 2. hdmi protocols require external circuitry to achieve compliance. s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 54 gth transceiver protocol jitter characteristics for table 58 through table 63 , the ultrascale architecture gt h transceiver user guide ( ug576 ) contains recommended settings for optimal usage of protocol specific characteristics. table 58: gigabit ethernet protocol characteristics (gth transceivers) description line rate (mb/s) min max units gigabit ethernet transmitter jitter generation total transmitter jitter (t_tj) 1250 ? 0.24 ui gigabit ethernet receiver high frequency jitter tolerance total receiver jitter tolerance 1250 0.749 ? ui table 59: xaui protocol characteristics (gth transceivers) description line rate (mb/s) min max units xaui transmitter jitter generation total transmitter jitter (t_tj) 3125 ? 0.35 ui xaui receiver high frequency jitter tolerance total receiver jitter tolerance 3125 0.65 ? ui table 60: pci express protocol characteristics (gth transceivers) (1) standard description condition line rate (mb/s) min max units pci express transmitter jitter generation pci express gen 1 total transmitter jitter 2500 ? 0.25 ui pci express gen 2 total transmitter jitter 5000 ? 0.25 ui pci express gen 3 (2) total transmitter jitter uncorrelated 8000 ? 31.25 ps deterministic transmitter jitter uncorrelated ? 12 ps pci express receiver high frequency jitter tolerance pci express gen 1 total receiver jitter tolerance 2500 0.65 ? ui pci express gen 2 (2) receiver inherent timing error 5000 0.40 ? ui receiver inherent deterministic timing error 0.30 ? ui pci express gen 3 (2) receiver sinusoidal jitter tolerance 0.03 mhz?1.0 mhz 8000 1.00 ? ui 1.0mhz?10mhz note 3 ?ui 10 mhz?100 mhz 0.10 ? ui notes: 1. tested per card electrom echanical (cem) methodology. 2. using common refclk. 3. between 1 mhz and 10 mhz the minimum sinusoidal jitter roll-off with a slope of 20 db/decade. s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 55 table 61: cei-6g and cei-11g protocol char acteristics (gth transceivers) description line rate (mb/s) interface min max units cei-6g transmitter jitter generation total transmitter jitter (1) 4976?6375 cei-6g-sr ? 0.3 ui cei-6g-lr ? 0.3 ui cei-6g receiver high frequency jitter tolerance total receiver jitter tolerance (1) 4976?6375 cei-6g-sr 0.6 ? ui cei-6g-lr 0.95 ? ui cei-11g transmitter jitter generation total transmitter jitter (2) 9950?11100 cei-11g-sr ? 0.3 ui cei-11g-lr/mr ? 0.3 ui cei-11g receiver high frequency jitter tolerance total receiver jitter tolerance (2) 9950?11100 cei-11g-sr 0.65 ? ui cei-11g-mr 0.65 ? ui cei-11g-lr 0.825 ? ui notes: 1. tested at most commonly used line rate of 6250 mb/s using 390.625 mhz reference clock. 2. tested at line rate of 9950 mb/s using 155.46875 mhz reference clock and 11100 mb/s using 173.4375 mhz reference clock. table 62: sfp+ protocol characteristics (gth transceivers) description line rate (mb/s) min max units sfp+ transmitter jitter generation total transmitter jitter 9830.40 (1) ?0.28ui 9953.00 10312.50 10518.75 11100.00 sfp+ receiver frequency jitter tolerance total receiver jitter tolerance 9830.40 (1) 0.7 ? ui 9953.00 10312.50 10518.75 11100.00 notes: 1. line rated used for cpri over sfp+ applications. s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 56 table 63: cpri protocol characteri stics (gth transceivers) description line rate (mb/s) min max units cpri transmitter jitter generation total transmitter jitter 614.4 ? 0.35 ui 1228.8 ? 0.35 ui 2457.6 ? 0.35 ui 3072.0 ? 0.35 ui 4915.2 ? 0.3 ui 6144.0 ? 0.3 ui 9830.4 ? note 1 ui cpri receiver frequency jitter tolerance total receiver jitter tolerance 614.4 0.65 ? ui 1228.8 0.65 ? ui 2457.6 0.65 ? ui 3072.0 0.65 ? ui 4915.2 0.95 ? ui 6144.0 0.95 ? ui 9830.4 note 1 ?ui notes: 1. tested per sfp+ specification, see table 62 . s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 57 gty transceiver specifications for the xcku095 gty transceiver dc input and output levels for the xcku095 table 64 summarizes the dc specifications of the gty transceivers in the xcku095 devices (only). consult www.xilinx.com/products/tec hnology/high-speed-serial for further details. table 64: gty transceiver dc specifications symbol dc parameter conditions min typ max units dv ppin differential peak-to-peak input voltage (external ac coupled) >10.3125 gb/s 150 ? 1250 mv 6.6 gb/s to 10.3125 gb/s 150 ? 1250 mv 6.6 gb/s 150 ? 2000 mv v in single-ended input voltage. voltage measured at the pin referenced to gnd. dc coupled v mgtavtt =1.2v ?400 ? v mgtavtt mv v cmin common mode input voltage dc coupled v mgtavtt =1.2v ?2/3v mgtavtt ?mv d vppout differential peak-to-peak output voltage (1) transmitter output swing is set to 0x1f 800 ? ? mv v cmoutdc common mode output voltage: dc coupled (equation based) when remote rx is terminated to gnd v mgtavtt /2 ? d vppout /4 mv when remote rx termination is floating v mgtavtt ? d vppout /2 mv when remote rx is terminated to v rx_term (2) mv v cmoutac common mode output voltage: ac coupled equation based v mgtavtt ? d vppout /2 mv r in differential input resistance ? 100 ? r out differential output resistance ? 100 ? t oskew transmitter output pair (txp and txn) intra-pair skew ? ? 5 ps c ext recommended external ac coupling capacitor (3) ? 100 ? nf notes: 1. the output swing and pre-emphasis levels are programmable using the gty transceiver attributes and can result in values lower than reported in this table. 2. v rx_term is the remote rx termination voltage. 3. other values can be used as appropriate to conform to specific protocols and standards. x-ref target - figure 6 figure 6: single-ended peak-to-peak voltage v mgtavtt d vppout 4 ----------------------- - ? v mgtavtt v rx_term ? 2 ------------------------------------------------------- - ?? ?? ? 0 +v p n ds892_03_ 120414 single-ended peak-to-peak voltage s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 58 table 65 summarizes the dc specifications of the clock input of the gty transceivers in the xcku095 devices (only). consult www.xilinx.com/products/techn ology/high-speed-serial for further details. x-ref target - figure 7 figure 7: differential peak-to-peak voltage table 65: gty transceiver clock dc input level specification symbol dc parameter min typ max units v idiff differential peak-to-peak input voltage 250 ? 2000 mv r in differential input resistance ? 100 ? c ext required external ac coupling capacitor ? 10 ? nf 0 +v ?v p?n ds892_04_ 120414 differential peak-to-peak voltage differential peak-to-peak voltage = (single-ended peak-to-peak voltage) x 2 s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 59 gty transceiver switching characteristics for the xcku095 consult www.xilinx.com/products/tec hnology/high-speed-serial for further information. table 66: gty transceiver performance symbol description output divider xcku095 speed grades and temperature range units -2e, -2i -1c, -1i f gtymax gty maximum line rate 16.375 12.5 gb/s f gtymin gty minimum line rate 0.5 0.5 gb/s min max min max f gtycrange cpll line rate range (1) 1 4.0 12.5 4.0 8.5 gb/s 2 2.0 6.25 2.0 4.25 gb/s 4 1.0 3.125 1.0 2.125 gb/s 8 0.5 1.5625 0.5 1.0625 gb/s min max min max f gtyqrange1 qpll0 line rate range 1 (2) 9.8 16.375 9.8 12.5 gb/s 2 (2) 4.9 8.1875 4.9 8.1875 gb/s 4 (2) 2.45 4.09375 2.45 4.09375 gb/s 8 (2) 1.225 2.04688 1.225 2.04688 gb/s 16 (2) 0.6125 1.02344 0.6125 1.02344 gb/s min max min max f gtyqrange2 qpll1 line rate range 1 (3) 8.013.08.012.5gb/s 2 (3) 4.0 6.5 4.0 6.5 gb/s 4 (3) 2.03.252.03.25gb/s 8 (3) 1.0 1.625 1.0 1.625 gb/s 16 (3) 0.5 0.8125 0.5 0.8125 gb/s min max min max f cpllrange cpll frequency range 2.0 6.25 2.0 4.25 ghz f qpll0range qpll0 frequency range 9.8 16.375 9.8 16.375 ghz f qpll1range qpll1 frequency range 8.0 13.0 8.0 13.0 ghz notes: 1. the values listed are the rounded results of the calculated equation (2 x cpll_frequency)/output_divider. 2. the values listed are rounded results from calc ulated equation (qpll0_frequency)/output_divider. 3. the values listed are rounded results from calc ulated equation (qpll1_frequency)/output_divider. table 67: gty transceiver dynamic reconfiguration port (drp) switching characteristics symbol description xcku095 units f gtydrpclk gtydrpclk maximum frequency 250 mhz s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 60 table 68: gty transceiver reference clock switching characteristics symbol description conditions min typ max units f gclk reference clock frequency range 60 ? 820 mhz t rclk reference clock rise time 20% ? 80% ? 200 ? ps t fclk reference clock fall time 80% ? 20% ? 200 ? ps t dcref reference clock duty cycle transceiver pll only 40 50 60 % x-ref target - figure 8 figure 8: reference clock timing parameters table 69: gty transceiver reference clock os cillator selection phase noise mask (1) symbol description offset frequency min typ max units qpll refclkmask qpll0/qpll1 reference clock select phase noise mask at refclk frequency = 156.25 mhz. 10 khz ? ? ?112 dbc/hz 100 khz ? ? ?128 1 mhz ? ? ?145 qpll0/qpll1 reference clock select phase noise mask at refclk frequency = 312.5 mhz. 10 khz ? ? ?103 dbc/hz 100 khz ? ? ?123 1 mhz ? ? ?143 qpll0/qpll1 reference clock select phase noise mask at refclk frequency =625 mhz. 10 khz ? ? ?98 dbc/hz 100 khz ? ? ?117 1 mhz ? ? ?140 cpll refclkmask cpll reference clock select phase noise mask at refclk frequency = 156.25 mhz. 10 khz ? ? ?112 dbc/hz 100 khz ? ? ?128 1 mhz ? ? ?145 50 mhz ? ? ?145 cpll reference clock select phase noise mask at refclk frequency = 312.5 mhz. 10 khz ? ? ?103 dbc/hz 100 khz ? ? ?123 1 mhz ? ? ?143 50 mhz ? ? ?145 cpll reference clock select phase noise mask at refclk frequency = 625 mhz. 10 khz ? ? ?98 dbc/hz 100 khz ? ? ?117 1 mhz ? ? ?140 50 mhz ? ? ?144 notes: 1. for reference clock frequencies not in this table, use th e phase-noise mask for the nearest reference clock frequency. ds892_05_ 120414 80% 20% t fclk t rclk s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 61 table 70: gty transceiver pll/lock time adaptation symbol description conditions min typ max units t lock initial pll lock ? ? 1 ms t dlock clock recovery phase acquisition and adaptation time for decision feedback equalizer (dfe). after the pll is locked to the reference clock, this is the time it takes to lock the clock data recovery (cdr) to the data present at the input. ? 50,000 37 x 10 6 ui clock recovery phase acquisition and adaptation time for low-power mode (lpm) when the dfe is disabled. ?50,0002.3x10 6 ui table 71: gty transceiver user clock switching characteristics (1) symbol description data width conditions (bit) speed grades and temperature ranges unit s internal logic interconnect logic -2e, -2i -1c, -1i f txoutpma txoutclk maximum frequency sourced from outclkpma 511.719 390.625 mhz f rxoutpma rxoutclk maximum frequency source d from outclkpma 511.719 390.625 mhz f txoutprogdiv txoutclk maximum frequency sourced from txprogdivclk 511.719 511.719 mhz f rxoutprogdiv rxoutclk maximum frequency sourced from rxprogdivclk 511.719 511.719 mhz f txin txusrclk maximum frequency 16 16, 32 511.719 390.625 mhz 32 32, 64 511.719 390.625 mhz 20 20, 40 409.375 312.500 mhz 40 40, 80 409.375 312.500 mhz f rxin rxusrclk maximum frequency 16 16, 32 511.719 390.625 mhz 32 32, 64 511.719 390.625 mhz 20 20, 40 409.375 312.500 mhz 40 40, 80 409.375 312.500 mhz f txin2 txusrclk2 maximum frequency 16 16 511.719 390.625 mhz 20 20 409.375 312.500 mhz 16, 32 32 511.719 390.625 mhz 20, 40 40 409.375 312.500 mhz 32 64 255.860 195.313 mhz 40 80 204.688 156.250 mhz f rxin2 rxusrclk2 maximum frequency 16 16 511.719 390.625 mhz 20 20 409.375 312.500 mhz 16, 32 32 511.719 390.625 mhz 20, 40 40 409.375 312.500 mhz 32 64 255.860 195.313 mhz 40 80 204.688 156.250 mhz notes: 1. clocking must be implem ented as described in the ultrascale architecture gt y transceiver user guide ( ug578 ). s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 62 table 72: gty transceiver transmitter switching characteristics symbol description condition min typ max units f gtytx serial data rate range 0.500 ? f gtymax gb/s t rtx tx rise time 20%?80% ? 40 ? ps t ftx tx fall time 80%?20% ? 40 ? ps t llskew tx lane-to-lane skew (1) ??500ps v txoobvdpp electrical idle amplitude ? ? 15 mv t txoobtransition electrical idle transition time ? ? 140 ns t j16.375_qpll total jitter (2)(4) 16.375 gb/s ? ? 0.28 ui d j16.375_qpll deterministic jitter (2)(4) ? ? 0.17 ui t j15.0_qpll total jitter (2)(4) 15.0 gb/s ? ? 0.28 ui d j15.0_qpll deterministic jitter (2)(4) ? ? 0.17 ui t j14.1_qpll total jitter (2)(4) 14.1 gb/s ? ? 0.28 ui d j14.1_qpll deterministic jitter (2)(4) ? ? 0.17 ui t j14.025_qpll total jitter (2)(4) 14.025 gb/s ? ? 0.28 ui d j14.025_qpll deterministic jitter (2)(4) ? ? 0.17 ui t j13.1_qpll total jitter (2)(4) 13.1 gb/s ? ? 0.28 ui d j13.1_qpll deterministic jitter (2)(4) ? ? 0.17 ui t j12.5_qpll total jitter (2)(4) 12.5 gb/s ? ? 0.28 ui d j12.5_qpll deterministic jitter (2)(4) ? ? 0.17 ui t j12.5_cpll total jitter (2)(4) 12.5 gb/s ? ? 0.33 ui d j12.5_cpll deterministic jitter (2)(4) ? ? 0.17 ui t j11.3_qpll total jitter (2)(4) 11.3 gb/s ? ? 0.28 ui d j11.3_qpll deterministic jitter (2)(4) ? ? 0.17 ui t j10.3125_qpll total jitter (2)(4) 10.3125 gb/s ? ? 0.28 ui d j10.3125_qpll deterministic jitter (2)(4) ? ? 0.17 ui t j10.3125_cpll total jitter (3)(4) 10.3125 gb/s ? ? 0.33 ui d j10.3125_cpll deterministic jitter (3)(4) ? ? 0.17 ui t j9.953_qpll total jitter (2)(4) 9.953 gb/s ? ? 0.28 ui d j9.953_qpll deterministic jitter (2)(4) ? ? 0.17 ui t j9.8_qpll total jitter (2)(4) 9.8 gb/s ? ? 0.28 ui d j9.8_qpll deterministic jitter (2)(4) ? ? 0.17 ui t j8.0_qpll total jitter (2)(4) 8.0 gb/s ? ? 0.28 ui d j8.0_qpll deterministic jitter (2)(4) ? ? 0.17 ui t j8.0_cpll total jitter (3)(4) 8.0 gb/s ? ? 0.32 ui d j8.0_cpll deterministic jitter (3)(4) ? ? 0.17 ui t j6.6_cpll total jitter (3)(4) 6.6 gb/s ? ? 0.30 ui d j6.6_cpll deterministic jitter (3)(4) ? ? 0.15 ui t j5.0 total jitter (3)(4) 5.0 gb/s ? ? 0.30 ui d j5.0 deterministic jitter (3)(4) ? ? 0.15 ui t j4.25 total jitter (3)(4) 4.25 gb/s ? ? 0.30 ui d j4.25 deterministic jitter (3)(4) ? ? 0.15 ui s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 63 t j4.00l total jitter (3)(4) 4.00 gb/s ? ? 0.32 ui d j4.00l deterministic jitter (3)(4) ? ? 0.16 ui t j3.75 total jitter (3)(4) 3.75 gb/s ? ? 0.20 ui d j3.75 deterministic jitter (3)(4) ? ? 0.10 ui t j3.20 total jitter (3)(4) 3.20 gb/s (5) ? ? 0.20 ui d j3.20 deterministic jitter (3)(4) ? ? 0.10 ui t j2.5 total jitter (3)(4) 2.5 gb/s (6) ? ? 0.20 ui d j2.5 deterministic jitter (3)(4) ? ? 0.10 ui t j1.25 total jitter (3)(4) 1.25 gb/s (7) ? ? 0.15 ui d j1.25 deterministic jitter (3)(4) ? ? 0.05 ui t j500 total jitter (3)(4) 500 mb/s ? ? 0.10 ui d j500 deterministic jitter (3)(4) ? ? 0.05 ui notes: 1. using same refclk input with tx phas e alignment enabled for up to four fully- populated gty quads at maximum line rate. 2. using qpll_fbdiv = 40, 20-bit internal data width. these va lues are not intended for pr otocol specific compliance determinations. 3. using cpll_fbdiv = 2, 20-bit internal da ta width. these values are not intend ed for protocol specific compliance determinations. 4. all jitter values are based on a bit-error ratio of 10 -12 . 5. cpll frequency at 3.2 ghz and txout_div = 2. 6. cpll frequency at 2.5 ghz and txout_div = 2. 7. cpll frequency at 2.5 ghz and txout_div = 4. table 73: gty transceiver receiver switching characteristics symbol description condition min typ max units f gtyrx serial data rate 0.500 ? f gtymax gb/s t rxelecidle time for rxelecidle to respond to loss or restoration of data ?10?ns r xoobvdpp oob detect threshold peak-to-peak 60 ? 150 mv r xsst receiver spread-spectrum tracking (1) modulated at 33 khz ?5000 ? 0 ppm r xrl run length (cid) ? ? 256 ui r xppmtol data/refclk ppm offset tolerance bit rates 6.6 gb/s ?1250 ? 1250 ppm bit rates > 6.6 gb/s and 8.0 gb/s ?700 ? 700 ppm bit rates > 8.0 gb/s ?200 ? 200 ppm sj jitter tolerance (2) j t_sj16.375 sinusoidal jitter (cpll) (3) 16.375 gb/s ? ? 0.30 ui j t_sj15.0 sinusoidal jitter (cpll) (3) 15.0 gb/s ? ? 0.30 ui j t_sj14.1 sinusoidal jitter (cpll) (3) 14.1 gb/s ? ? 0.30 ui j t_sj13.1 sinusoidal jitter (cpll) (3) 13.1 gb/s ? ? 0.30 ui j t_sj12.5_qpll sinusoidal jitter (cpll) (3) 12.5 gb/s ? ? 0.30 ui j t_sj12.5_cpll sinusoidal jitter (cpll) (3) 12.5 gb/s ? ? 0.30 ui j t_sj11.3 sinusoidal jitter (cpll) (3) 11.3 gb/s ? ? 0.30 ui j t_sj10.32_qpll sinusoidal jitter (cpll) (3) 10.32 gb/s ? ? 0.30 ui table 72: gty transceiver transmitter switching characteristics (cont?d) symbol description condition min typ max units s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 64 j t_sj10.32_cpll sinusoidal jitter (cpll) (3) 10.32 gb/s ? ? 0.30 ui j t_sj9.8 sinusoidal jitter (cpll) (3) 9.8 gb/s ? ? 0.30 ui j t_sj8.0_qpll sinusoidal jitter (cpll) (3) 8.0 gb/s ? ? 0.44 ui j t_sj8.0_cpll sinusoidal jitter (cpll) (3) 8.0 gb/s ? ? 0.42 ui j t_sj6.6_cpll sinusoidal jitter (cpll) (3) 6.6 gb/s ? ? 0.44 ui j t_sj5.0 sinusoidal jitter (cpll) (3) 5.0 gb/s ? ? 0.44 ui j t_sj4.25 sinusoidal jitter (cpll) (3) 4.25 gb/s ? ? 0.44 ui j t_sj4.00l sinusoidal jitter (cpll) (3) 4.0 gb/s ? ? 0.45 ui j t_sj3.75 sinusoidal jitter (cpll) (3) 3.75 gb/s ? ? 0.45 ui j t_sj3.20 sinusoidal jitter (cpll) (3) 3.2 gb/s (4) ??0.45ui j t_sj2.5 sinusoidal jitter (cpll) (3) 2.5 gb/s (5) ??0.50ui j t_sj1.25 sinusoidal jitter (cpll) (3) 1.25 gb/s (6) ??0.50ui j t_sj500 sinusoidal jitter (cpll) (3) 500 mb/s ? ? 0.50 ui sj jitter tolerance with stressed eye (2) j t_tjse3.2 total jitter with stressed eye (7) 3.2 gb/s ? ? 0.7 ui j t_tjse6.6 6.6 gb/s ? ? 0.7 ui j t_sjse3.2 sinusoidal jitter with stressed eye (7) 3.2 gb/s ? 0.7 ui j t_sjse6.6 6.6 gb/s ? 0.7 ui notes: 1. using rxout_div = 1, 2, and 4. 2. all jitter values are based on a bit error ratio of 10 ?12 . 3. the frequency of the injected sinusoidal jitter is 80 mhz. 4. cpll frequency at 3.2 ghz and rxout_div = 2. 5. cpll frequency at 2.5 ghz and rxout_div = 2. 6. cpll frequency at 2.5 ghz and rxout_div = 4. 7. composite jitter with rx equalizer enabled. dfe disabled. table 73: gty transceiver receiver switching characteristics (cont?d) symbol description condition min typ max units s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 65 gty transceiver electrical compliance for the xcku095 the ultrascale archit ecture gty transceiver user guide ( ug578 ) contains recommended use modes that ensure compliance for the protocols listed in table 74 . the transceiver wizard provides the recommended settings for those use cases and for protocol specific characteristics. table 74: gty transceiver protocol list protocol specification serial rate (gb/s) electrical compliance interlaken oif-cei-6g, oif- cei-11gsr 4.25?12.5 compliant caui-10 ieee 802.3-2012 10.3125 compliant nppi ieee 802.3-2012 10.3125 compliant 10gbase-kr ieee 802.3-2012 10.3125 compliant sfp+ sff-8431 (sr and lr) 9.95328?11.10 compliant xfp inf-8077i, revision 4.5 10.3125 compliant rxaui cei-6g-sr 6.25 compliant xaui ieee 802.3-2012 3.125 compliant 1000base-x ieee 802.3-2012 1.25 compliant otu2 itu g.8251 10.709225 compliant otu4 (otl4.10) oif-cei-11g-sr 11.180997 compliant oc-3/12/48/192 gr-253-core 0.1555?9.956 compliant pcie gen1, 2, 3 pci express base 3.0 2.5, 5.0, and 8.0 compliant sdi smpte 424m-2006 0.27?2.97 compliant hybrid memory cube (hmc) hmc-15g-sr 12.5 and 15.0 compliant cpri cpri_v_6_1_2014-07-01 0.6144?12.165 compliant passive optical network (pon) 10g-epon, 1g-epon, ng-pon2, xg-pon, and 2.5g-pon 0.155?10.3125 compliant jesd204a/b oif-cei-6g, oif-cei-11g 3.125?12.5 compliant serial rapidio rapidio specification 3.1 1.25?10.3125 compliant displayport (source only) dp 1.2b cts 1.62?5.4 compliant fibre channel fc-pi-4 1.0625?14.025 compliant sata gen1, 2, 3 serial ata revision 3.0 specification 1.5, 3.0, and 6.0 compliant sas gen1, 2, 3 t10/bsr incits 519 3.0, 6.0, and 12.0 compliant sfi-5 oif-sfi5-01.0 0.625 - 12.5 compliant s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 66 gty transceiver protocol jitter characteristics for the xcku095 for table 75 through table 79 , the ultrascale architecture gty transceiver user guide ( ug578 ) contains recommended settings for optimal usage of protocol specific characteristics. table 75: gigabit ethernet protocol characteristics (gty transceivers) description line rate (mb/s) min max units gigabit ethernet transmitter jitter generation total transmitter jitter (t_tj) 1250 ? 0.24 ui gigabit ethernet receiver high frequency jitter tolerance total receiver jitter tolerance 1250 0.749 ? ui table 76: xaui protocol characteristics (gty transceivers) description line rate (mb/s) min max units xaui transmitter jitter generation total transmitter jitter (t_tj) 3125 ? 0.35 ui xaui receiver high frequency jitter tolerance total receiver jitter tolerance 3125 0.65 ? ui table 77: cei-6g and cei-11g protocol char acteristics (gty transceivers) description line rate (mb/s) interface min max units cei-6g transmitter jitter generation total transmitter jitter (1) 4976?6375 cei-6g-sr ? 0.3 ui cei-6g-lr ? 0.3 ui cei-6g receiver high frequency jitter tolerance total receiver jitter tolerance (1) 4976?6375 cei-6g-sr 0.6 ? ui cei-6g-lr 0.95 ? ui cei-11g transmitter jitter generation total transmitter jitter (2) 9950?11100 cei-11g-sr ? 0.3 ui cei-11g-lr/mr ? 0.3 ui cei-11g receiver high frequency jitter tolerance total receiver jitter tolerance (2) 9950?11100 cei-11g-sr 0.65 ? ui cei-11g-mr 0.65 ? ui cei-11g-lr 0.825 ? ui notes: 1. tested at most commonly used line rate of 6250 mb/s using 390.625 mhz reference clock. 2. tested at line rate of 9950 mb/s using 155.46875 mhz reference clock and 11100 mb/s using 173.4375 mhz reference clock. s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 67 table 78: sfp+ protocol characteristics (gty transceivers) description line rate (mb/s) min max units sfp+ transmitter jitter generation total transmitter jitter 9830.40 (1) ?0.28ui 9953.00 10312.50 10518.75 11100.00 sfp+ receiver frequency jitter tolerance total receiver jitter tolerance 9830.40 (1) 0.7 ? ui 9953.00 10312.50 10518.75 11100.00 notes: 1. line rated used for cpri over sfp+ applications. table 79: cpri protocol characteristics (gty transceivers) description line rate (mb/s) min max units cpri transmitter jitter generation total transmitter jitter 614.4 ? 0.35 ui 1228.8 ? 0.35 ui 2457.6 ? 0.35 ui 3072.0 ? 0.35 ui 4915.2 ? 0.3 ui 6144.0 ? 0.3 ui 9830.4 ? note 1 ui cpri receiver frequency jitter tolerance total receiver jitter tolerance 614.4 0.65 ? ui 1228.8 0.65 ? ui 2457.6 0.65 ? ui 3072.0 0.65 ? ui 4915.2 0.95 ? ui 6144.0 0.95 ? ui 9830.4 note 1 ?ui notes: 1. tested per sfp+ specification, see table 78 . s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 68 integrated interface block for interlaken for the xcku095 more information and documentation on solutions usin g the integrated interface block for interlaken can be found at ultrascale interlaken . integrated interface block for 100g ethernet mac and pcs for the xcku095 more information and documentation on solutions us ing the integrated 100 gb/s ethernet block can be found at ultrascale integrated 100g ethernet mac/pcs . table 80: maximum performance for interlaken designs symbol description speed grades and v ccint operating voltage units 0.95v -2 -1 f rx_serdes_clk receive serializer/ deserializer clock 195.32 195.32 mhz f tx_serdes_clk transmit serializer/ deserializer clock 195.32 195.32 mhz f drp_clk dynamic reconfiguration port clock 250.00 250.00 mhz min max min max f core_clk interlaken core clock 300.00 322.27 300.00 322.27 mhz f lbus_clk interlaken local bus clock 300.00 322.27 300.00 322.27 mhz table 81: maximum performance for 100g ethernet designs symbol description speed grades and v ccint operating voltage units 0.95v -2 -1 f tx_clk transmit clock 322.27 322.27 mhz f rx_clk receive clock 322.27 322.27 mhz f rx_serdes_clk receive serializer/deserializer clock 322.27 322.27 mhz f drp_clk dynamic reconfiguration port clock 250.00 250.00 mhz s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 69 integrated interface block for pci express designs more information and documentation on soluti ons for pci express designs can be found at pci express . system monitor specifications table 82: maximum performance for pci express designs symbol description speed grades and v ccint operating voltages units 1.0v 0.95v 0.90v -3 -2 -1 -1l -1l f pipeclk pipe clock maximum frequency 250.00 250.00 250.00 250.00 250.00 mhz f coreclk core clock maximum frequency 500.00 500.00 500.00 (1) 250.00 250.00 mhz f userclk user clock maximum frequency 250.00 250.00 250.00 250.00 250.00 mhz f drpclk drp clock maximum frequency 250.00 250.00 250.00 250.00 250.00 mhz notes: 1. pci express x8 gen 3 operation is supported in -2 and -3 speed grades. refer to the ultrascale architecture gen3 integrated block for pci express v4.0 user guide ( pg156 ) for information regarding x8 ge n 3 operation in the -1 speed grade. table 83: sysmon specifications parameter symbol comments/conditions min typ max units v ccadc = 1.8v 3%, v refp = 1.25v, v refn = 0v, adcclk = 5.2 mhz, t j = ?40c to 100c, typical values at t j = 40c adc accuracy (1) resolution 10 ? ? bits integral nonlinearity (2) inl ? ? 2 lsbs differential nonlinearity dnl no missing codes, guaranteed monotonic ??1lsbs offset error offset calibration enabled ? ? 2 lsbs gain error ??0.4% sample rate ??0.2ms/s rms code noise external 1.25v reference ? ? 1 lsbs on-chip reference ? 1 ? lsbs adc accuracy at extended temperatures resolution t j = ?55c to 125c 10 ? ? bits integral nonlinearity inl t j = ?55c to 125c ? ? 2 lsbs differential nonlinearity dnl no missing codes, guaranteed monotonic t j = ?55c to 125c ??1 s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 70 analog inputs (2) adc input ranges unipolar operation 0 ? 1 v bipolar operation ?0.5 ? +0.5 v unipolar common mode range (fs input) 0 ? +0.5 v bipolar common mode range (fs input) +0.5 ? +0.6 v maximum external channel input ranges adjacent channels set within these ranges should not corrupt measurements on adjacent channels ?0.1 ? v ccadc v on-chip sensor accuracy temperature sensor error (1) t j = ?40c to 100c (with external ref) ? ? 4 c t j = ?55c to 125c (with external ref) ? ? 4.5 c t j = ?40c to 100c (with internal ref) ? ? 5 c t j = ?55c to 125c (with internal ref) ? ? 6.5 c supply sensor error (3) t j = ?40c to 100c (with external ref) ? ? 1 % t j = ?55c to 125c (with external ref) ? ? 2 % t j = ?40c to 100c (with internal ref) ? ? 1.5 % t j = ?55c to 125c (with internal ref) ? ? 2.5 % conversion rate (4) conversion time?continuous t conv number of adcclk cycles 26 ? 32 cycles conversion time?event t conv number of adcclk cycles ? ? 21 cycles drp clock frequency dclk drp clock frequency 8 ? 250 mhz adc clock frequency adcclk derived from dclk 1 ? 5.2 mhz dclk duty cycle 40 ? 60 % sysmon reference (5) external reference v refp externally supplied reference voltage 1.20 1.25 1.30 v on-chip reference ground v refp pin to agnd, -2 and -3 speed grade t j = ?40c to 100c 1.2375 1.25 1.2625 v ground v refp pin to agnd, -1 and -1l speed grade t j = ?40c to 100c 1.23125 1.25 1.26875 v ground v refp pin to agnd, t j = ?55c to 125c 1.225 1.25 1.275 v notes: 1. adc offset errors are removed by enabling the adc automatic offset calibration feature. the values are specified for when this feature is enabled. 2. see the analog input section in the ultrascale architecture system monitor user guide ( ug580 ). 3. supply sensor offset and gain errors ar e removed by enabling the automatic offset and gain calibration feature. the values are specified for when th is feature is enabled. 4. see the adjusting the acquisition settling time section in the ultrascale architecture sy stem monitor user guide ( ug580 ). 5. any variation in the reference voltage from the nominal v refp = 1.25v and v refn = 0v will result in a deviation from the ideal transfer function. this also impacts the accuracy of th e internal sensor measurements (i.e., temperature and power supply). however, for external ratiometric type applicat ions allowing reference to vary by 4% is permitted. table 83: sysmon specifications (cont?d) parameter symbol comments/conditions min typ max units s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 71 i2c interfaces table 84: i2c fast mode interface switching characteristics (1) symbol description min typ max units t dcfclk scl duty cycle ? 50 ? % t fcko sdao clock-to-out delay ? ? 900 ns t fdck sdai setup time 100 ? ? ns f fclk scl clock frequency ? ? 400 khz notes: 1. test conditions: lvcmos33, slow slew rate, 8 ma drive strength, 15 pf loads. x-ref target - figure 9 figure 9: i2c fast mode interface timing diagram table 85: i2c standard mode interface switching characteristics (1) symbol description min typ max units t dcsclk scl duty cycle ? 50 ? % t scko sdao clock-to-out delay ? ? 3450 ns t sdck sdai setup time 250 ? ? ns f sclk scl clock frequency ? ? 100 khz notes: 1. test conditions: lvcmos33, slow slew rate, 8 ma drive strength, 15 pf loads. x-ref target - figure 10 figure 10: i2c standard mode interface timing diagram t fcko t fdck ds 892 _06_120414 scl sdai sdao t scko t sdck ds 892 _07_120414 scl sdai sdao s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 72 configuration switching characteristics table 86: configuration switching characteristics symbol description speed grades and v ccint operating voltages units 1.0v 0.95v 0.90v -3 -2 -1 -1l -1l power-up timing characteristics t pl program latency 7.5 7.5 7.5 7.5 7.5 ms, max t por power-on reset (40 ms ramp rate time) 57 57 57 57 57 ms, max 00000ms, min power-on reset with por override (2 ms ramp rate time) 15 15 15 15 15 ms, max 55555ms, min t program program pulse width 250 250 250 250 250 ns, min cclk output (master mode) t icck master cclk output delay from init_b 150 150 150 150 150 ns, min t mcckl (1) master cclk clock low time duty cycle 40/60 40/60 40/60 40/60 40/60 %, min/max t mcckh master cclk clock high time duty cycle 40/60 40/60 40/60 40/60 40/60 %, min/max f mcck master cclk frequency spi x2/x4/x8 bpi x8/x16 150 150 150 150 150 mhz, max spi x1 and serial slr-based devices 125 125 125 125 125 mhz, max spi x1 and serial all other devices 150 150 150 150 150 mhz, max selectmap 125 125 125 125 125 mhz, max f mcck_start master cclk frequency at start of configuration 33333mhz, typ f mccktol frequency tolerance, master mode with respect to nominal cclk 35 35 35 35 35 %, max cclk input (slave modes) t scckl slave cclk clock minimum low time 2.5 2.5 2.5 2.5 2.5 ns, min t scckh slave cclk clock minimum high time 2.5 2.5 2.5 2.5 2.5 ns, min f scck slave cclk frequency serial slr-based 125 125 125 125 125 mhz, max serial all other devices 150 150 150 150 150 mhz, max selectmap 125 125 125 125 125 mhz, max s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 73 emcclk input (master mode) t emcckl external master cclk low time 2.5 2.5 2.5 2.5 2.5 ns, min t emcckh external master cclk high time 2.5 2.5 2.5 2.5 2.5 ns, min f emcck external master cclk frequency spi x2/x4/x8 bpi x8/x16 150 150 150 150 150 mhz, max spi x1, serial slr-based 125 125 125 125 125 mhz, max spi x1, serial all other devices 150 150 150 150 150 mhz, max selectmap 125 125 125 125 125 mhz, max internal configuration access port f icapck internal configuration access port (icape3) master slr icap accessing the entire device 125 125 125 125 125 mhz, max slr icap accessing the local slr 200 200 200 200 200 mhz, max all other devices 200 200 200 200 200 mhz, max master/slave serial mode programming switching t dcck /t cckd d in setup/hold 3.0/0 3.0/0 3.0/0 3.0/0 3.0/0 ns, min t cco d out clock to out 88888ns, max selectmap mode programming switching t smdcck /t smcckd d[31:00] setup/hold 3.5/0 3.5/0 3.5/0 3.5/0 3.5/0 ns, min t smcscck /t smcckcs csi_b setup/hold 4.0/0 4.0/0 4.0/0 4.0/0 4.0/0 ns, min t smwcck /t smcckw rdwr_b setup/hold 10.0/0 10.0/0 10.0/0 10.0/0 10.0/0 ns, min t smckcso cso_b clock to out (330 pull-up resistor required) 77777ns, max t smco d[31:00] clock to out in readback 88888ns, max f rbcck readback frequency slr-based 125 125 125 125 125 mhz, max all other devices 125 125 125 125 125 mhz, max boundary-scan port timing specifications t taptck /t tcktap tms and tdi setup/hold slr-based 7.0/ 2.0 7.0/ 2.0 7.0/ 2.0 7.0/ 2.0 7.0/ 2.0 ns, min all other devices 3.0/ 2.0 3.0/ 2.0 3.0/ 2.0 3.0/ 2.0 3.0/ 2.0 ns, min t tcktdo tck falling edge to tdo output slr-based 1010101010 ns, max all other devices77777ns, max f tck tck frequency slr-based 2020202020mhz, max xcku095 5050505050mhz, max all other devices6666666666mhz, max table 86: configuration switching characteristics (cont?d) symbol description speed grades and v ccint operating voltages units 1.0v 0.95v 0.90v -3 -2 -1 -1l -1l s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 74 bpi master flash mode programming switching t bpicco a[28:00], rs[1:0], fcs_b, foe_b, fwe_b, adv_b clock to out 10 10 10 10 10 ns, max t bpidcc /t bpiccd d[15:00] setup/hold 3.5/0 3.5/0 3.5/0 3.5/0 3.5/0 ns, min spi master flash mode programming switching t spidcc /t spiccd d[03:00] setup/hold 3.0/0 3.0/0 3.0/0 3.0/0 3.0/0 ns, min t spidcc /t spiccd d[07:04] setup/hold 3.5/0 3.5/0 3.5/0 3.5/0 3.5/0 ns, min t spiccm mosi clock to out 8.0 8.0 8.0 8.0 8.0 ns, max t spiccfc fcs_b clock to out 8.0 8.0 8.0 8.0 8.0 ns, max dna port switching f dnack dna port frequency 200 200 200 200 200 mhz, max startupe3 ports t usrcclko startupe3 usrcclko input port to cclk pin output delay 1.00/ 6.00 1.00/ 6.70 1.00/ 7.50 1.00/ 7.50 1.00/ 7.50 ns, min/max t do do[3:0] ports to d03-d00 pins output delay 1.00/ 6.70 1.00/ 7.70 1.00/ 8.40 1.00/ 8.40 1.00/ 8.40 ns, min/max t dts dts[3:0] ports to d03-d00 pins 3-state delays 1.00/ 7.30 1.00/ 8.30 1.00/ 9.00 1.00/ 9.00 1.00/ 9.00 ns, min/max t fcsbo fcsbo port to fcs_b pin output delay 1.00/ 6.90 1.00/ 8.00 1.00/ 8.60 1.00/ 8.60 1.00/ 8.60 ns, min/max t fcsbts fcsbts port to fcs_b pin 3-state delay 1.00/ 6.90 1.00/ 8.00 1.00/ 8.60 1.00/ 8.60 1.00/ 8.60 ns, min/max t usrdoneo usrdoneo port to done pin output delay 1.00/ 8.50 1.00/ 9.60 1.00/ 10.40 1.00/ 10.40 1.00/ 10.40 ns, min/max t usrdonets usrdonets port to done pin 3-state delay 1.00/ 8.50 1.00/ 9.60 1.00/ 10.40 1.00/ 10.40 1.00/ 10.40 ns, min/max t di d03-d00 pins to di[3:0] ports input delay 0.5/ 2.6 0.5/ 3.1 0.5/ 3.5 0.5/ 3.5 0.5/ 3.5 ns, min/max f cfgmclk startupe3 cfgmclk output frequency 5050505050mhz, typ f cfgmclktol startupe3 cfgmclk output frequency tolerance 15 15 15 15 15 %, max startup timing t dci_match specifies a stall in the startup cycle until the digitally controlled impedance (dci) match signals are asserted. 44444ms, max notes: 1. when the cclk is sourced from the emcclk pin with a di vide-by-one setting, the extern al emcclk must meet this duty-cycle requirement. table 86: configuration switching characteristics (cont?d) symbol description speed grades and v ccint operating voltages units 1.0v 0.95v 0.90v -3 -2 -1 -1l -1l s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 75 efuse programming conditions revision history the following table shows the revision history for this document. table 87: efuse programming conditions (1) symbol description min typ max units i fs v ccaux supply current ? ? 115 ma t j temperature range ?40 ? 125 c notes: 1. do not program efuse during device conf iguration (e.g., during configuration, during configuration readback, or when readback crc is active). date version description of revisions 04/01/2016 1.12 updated table 20 , table 21 , and table 22 to production release in vivado design suite 2016.1 of the following devices/speed/temper ature grades. with these changes, the xc kintex ultrascale family is production released. xcku085: -1l (0.95v) and -1l (0.90v) devices xcku115: -1l (0.95v) and -1l (0.90v) devices in table 26 , added lpddr3, updated the package fields, increased the ddr4 and ddr3l memory phy rates in the fbva676/ sfva784 pa ckages, added lrdimms to the notes, and removed note 7. in addition, the qdriv-xp is only for hp i/o banks. updated v meas for lvcmos and lvttl in table 30 . in table 32 , added the block ram and fifo clock-to-out delays section. added table 69 . 12/16/2015 1.11 updated the power-on/off power supply sequencing section. updated table 20 to speed specification 2015.4.1. increased the f gthmax for -1li (0.90v) in table 49 and added note 1 . updated the -1li (0.90v) column in table 54 . 11/24/2015 1.10.1 updated table 20 , table 21 , and table 22 to production release of the following devices/speed grades. xcku060: -3e and -1l (0.90v) devices xcku085: -3e devices xcku115: -3e devices xcku035: all speed grades in the sfva784 package xcku040: all speed grades in the sfva784 package added note 1 to table 22 . updated table 38 through table 43 with speed specifications for vivado design suite 2015.4. in table 45 , added the value for package skew on the xcku095 ffva1156. s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 76 10/12/2015 1.9 updated data in table 6 (xcku025, xcku085, and xcku095) and table 7 (xcku095). updated the description in power-on/off power supply sequencing . updated table 21 and table 22 to production release of the following devices/speed grades. xcku025: -1c/-1i and -2e/-2i devices xcku035: -1li (0.95v) and -1li (0.90v) xcku040: -1li (0.95v) and -1li (0.90v) xcku060: -1li (0.95v) xcku085: -1c/-1i and -2e/-2i devices xcku095: -1c/-1i and -2e/-2i devices updated table 20 , table 21 , table 22 , table 32 , table 33 , table 34 , table 38 through table 43 , and table 86 with speed specifications for vivado design suite 2015.3. updated table 45 with package skew data. added protocols to table 57 . updated v cmoutdc in table 64 . added data to table 72 and table 73 . added startup timing to table 86 . 09/22/2015 1.8 added gty tables to support the xcku095. added the xcku025 device. in table 2 , revised the -1l (0.90v) v ccint and v ccint_io for a recommended 20mv power supply operating range. updated description of i ccadc . updated table 21 and table 22 to production release of the -1 and -2 speed grade xcku115 devices and production release of the -3 speed grade for the xcku035 and xcku040 devices. updated table 20 , table 21 , table 22 , table 32 , table 34 , table 38 through table 43 , and table 86 with speed specifications for vivado design suite 2015.2.1. updated table 26 with more delineated values including adding package variations. in table 45 added the xcku095 ffva1156 pack age and updated skew values. updated protocols in table 57 . revised the values in table 80 and removed note 1. updated table 83 : sample rate . in table 86 , added further delineation between de vices (slr-based, xcku095, and all other devices), added values by speed grade, and updated -1l specifications. 08/03/2015 1.7 updated and added device information in table 7 . in table 18 and table 19 updated note 2 , note 3 , and note 4 . updated table 21 and table 22 to production release of the -1 and -2 speed grade xcku060 devices. updated table 20 , table 21 , table 22 , table 32 , table 34 , table 38 through table 43 , and table 86 with speed specifications for vivado design suite 2015.2 v1.17. added table 52 : gth transceiver reference clock oscillator selection phase noise mask . added the gth transceiver electrical compliance section. revised f coreclk and note 1 in table 82 . updated the startupe3 ports descriptions in table 86 . updated note 1 in table 87 . 05/12/2015 1.6 the minimum software requirements changed for ku040 requiring vivado design suite 2015.1 v1.15 per the design advisory answer record ar64347 : design advisory for ultrascale speed specification - 2015.1 production speed specification changes . this includes revisions to table 20 , table 21 , table 22 , table 27 , table 28 , and table 38 to table 43 . also, in table 29 , revised the hr i/o values for t outbuf_delay_te_pad and added note 1 . updated table 21 and table 22 to production release of the xcku035 devices in the fbva676 and ffva1156 packages. added note 2 to table 3 . clarifying edits to table 30 and table 31 . added note 1 to table 80 . updated the on-chip sensor accuracy in table 83 . in table 86 , added more specifications to the startupe3 ports section. date version description of revisions s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 77 02/24/2015 1.5 in table 1 , added i dc and i rms and updates to the gth and gty transceivers i dcin/out section including adding note 9 . added many specifications and recommended values to table 3 . updated specifications in table 4 , table 5 , and table 6 . added table 7 . revised the v ocm maximum for mini_lvds_25 and rsds_25 in table 12 . revised the v icm specifications in table 14 . removed rows from table 16 and table 17 . removed v oh and v ol rows, revised the v ocm maximum, and revised v icm in table 18 . removed v oh and v ol rows and revised v icm in table 19 . updated the following tables specifically addressing fbva900 design specifications; table 21 , table 22 , table 45 , and table 49 . removed table 27. updated table 20 , table 21 , table 22 , table 27 , and table 28 with speed specifications for vivado design suite 2014.4.1. completely revised the performance characteristics section including adding table 23 , table 24 , and table 25 , updating table 26 (including note 7), and removing table 27: maximum physical interface (phy) rate for memory interfaces (fbv packages) . added the section: i/o standard adjustment measurement methodology . revised f refclk in table 33 . revised mmcm_t lockmax in table 36 . revised the f inmax in table 36 and table 37 . updated table 44 . updated devices listed, packag es listed, and package skew in table 45 . updated v cmoutdc and d vppout in table 46 . added table 48 . table 49 . added new values and descriptions to both table 55 and table 56 . updated the f drp_clk in table 80 , table 81 , and table 82 . added to f core_clk and f userclk table 80 . updated on-chip reference and note 5 in table 83 . updated the f emcck , f scck , f mcck , t por , and t usrcclko specifications in table 86 . 11/14/2014 1.4 updated note 2 and note 3 in table 1 and note 3 , note 4 , and note 6 in table 2 . updated note 3 in table 6 . revised the power-on/off power supply sequencing section. updated the descriptions in table 8 . removed note 1 from both table 26 and table 27. revised ddr3 specification for fbva900 package -2i speed grade in table 27. updated table 20 , table 27 , and table 28 with speed specifications for vivado design suite 2014.3. updated the descriptions in table 37 . added a discussion on the data in the device pin-to-pin parameter tables on page 40 and page 42 . revised the values for f lbus_clk in table 80 . updated note 5 in table 83 . in table 86 , added more speed specifications, updated t pl , f mccktol , and f rbcck , added the startupe3 ports section, and added note 1 . 07/10/2014 1.3 updated lvdci_15 information in table 10 . revised the slvs_400 values in table 12 . updated table 20 and all the tables relevant to the latest speed specification vivado 2014.2 v1.08. removed rldram ii from table 26 and table 27. also added fbv package to table 27. removed t delay_rst_rdy from table 33 . revised mmcm_f induty in table 36 and pll_f induty in table 37 . updated the v in description in table 46 . updated figure 3 and figure 4 . updated note 1 in table 55 . added two new sections for the integrated interface block for interlaken for the xcku095 and the integrated interface block for 100g ethernet mac and pcs for the xcku095 . 05/16/2014 1.2 updated note 2 , added i ol and i oh specifications, and added note 3 and note 4 to table 9 and table 10 . in table 12 , revised the mini_lvds_25 and rsds_25 maximum value for v ocm and added slvs_400 specifications. in table 13 and table 14 , added the i ol and i oh specifications. removed the pod standards from table 10 and table 14 . updated the ac switching characteristics section and table 20 based upon the vivado design suite 2014.1 v1.06 speed specifications. updated t pw_wf_nc in table 32 . revised mmcm_t fbdelay in table 36 , and added pll_f bandwidth to table 37 . updated format and notes in table 42 and table 43 . revised notes in table 49 . updated value for f gthdrpclk in table 50 . updated the 0.90v values for f txoutprogdiv and f rxoutprogdiv in table 54 , and the corresponding f max in table 35 . in table 83 , updated on-chip sensor accuracy section, removed gain error conditions, updated note 1 , and added note 3 . in table 86 , revised t por specifications and updated f mcck , f scck , f icapck , f rbcck , t taptck /t tcktap , t tcktdo , and f tck . date version description of revisions s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 78 04/09/2014 1.1 added i dc and i rms to table 1 . in table 3 , updated the programmable input termination resistance sections (r), added note 5 and note 6 , and added the internal v ref and differential termination specifications. in table 8 , updated note 3 . revised the lvcmos15 v oh /v ol specifications in table 9 and table 10 . in table 12 , removed support for sub_lvds_25 and revised the v ocm values. instead sub_lvds will be supported in both hr and hp i/o banks. replaced sub_lvds_25 in table 27 with sub_lvds . in table 26 , split the -2 speed specifications by temperature range and updated the ddr3 and rldram iii specifications. in table 27, updated the -1 and -3 speed grade maximum specifications for ddr4. updated the speed specifications in table 27 and table 28 . removed table 24: clb switching characteristics which contained f tog (the toggle frequency). revised table 32 including adding t pw_wf_nc , t pw_rf , and note 1 . updated table 33 especially f refclk , t minper_rst , and the idelay/odelay chain resolution. replaced all the tables in the clock buffers and networks section with table 35 . updated the mmcm_f pfdmax in table 36 . updated the pll_f pfdmax and the pll_t outduty in table 37 . changed the d vppout value to minimum in table 46 . updated the typical c ext value in table 47 . in table 49 , increased the f gthqrange1 maximum for the 16 output dividers in the -1 speed grade, and added note 2 and note 3 . in table 54 , updated four rows of txoutclk/rxoutclk information and removed note 2, note 3, and note 4. revised the t llskew value and units in table 55 . updated the notes in table 60 . in table 83 , revised the inl maximum and adc accuracy at extended temperatures and updated some of the on-chip sensor accuracy maximum values. revised f mcck and updated the ramp rate for t por in table 86 . 12/10/2013 1.0 initial xilinx release. date version description of revisions s e n d f e e d b a c k
kintex ultrascale fpgas data sheet: dc and ac switching characteristics ds892 (v1.12) april 1, 2016 www.xilinx.com product specification 79 notice of disclaimer the information disclosed to you hereunder (the ?materials?) is provided solely for the selectio n and use of xilinx products. t o the maximum extent permitted by applicable law: (1) materials are ma de available "as is" and with al l faults, xilinx hereby disclai ms all warranties and conditions, express, implied, or statutory, including but no t limited to warranties of merchantability, non-infringement, or fitness for any partic ular purpose; and (2) xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) fo r any loss or damage of any kind or nature related to, arising under, or in connection with, th e materials (including your use of the ma terials), including for any direct, indire ct, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or xilinx h ad been advised of the possibility of the same . xilinx assumes no obligation to correct an y errors contained in the materials or t o notify you of updates to the mate rials or to product specifications. you may not reproduce, modify, distribute, or publicly dis play the materials without prior written consent. certain products are subject to the terms and conditio ns of xilinx?s limited warra nty, please refer to xilinx?s terms of sale which can be viewed at www.xilinx.com/legal.htm#tos ; ip cores may be subject to warranty and support terms contained in a license issued to you by xilinx. xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-saf e performance; you assume sole risk and lia bility for use of xilinx products in su ch critical applications, please refer to xilinx?s terms of sale which can be viewed at www.xilinx.com/legal.htm#tos . automotive applications disclaimer xilinx products are not designed or intended to be fail-safe, or for use in any application requiring fail-safe performance, such as applications related to: (i) the de ployment of airbags, (ii) control of a vehicle, unless there is a fail-safe or redundancy feature (which does not include use of software in the xilinx device to implement the redundancy) and a warnin g signal upon failure to the operator, or (iii) uses that could lead to death or personal injury. customer assumes the sole risk and liability of any use of xilinx products in such applications. s e n d f e e d b a c k

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